arch: Enable `FEAT_SB` for supported non-Armv8.5-A platforms

The speculation barrier feature (`FEAT_SB`) was introduced with and
made mandatory in the Armv8.5-A extension. It was retroactively made

arch: Enable `FEAT_SB` for supported non-Armv8.5-A platforms

The speculation barrier feature (`FEAT_SB`) was introduced with and
made mandatory in the Armv8.5-A extension. It was retroactively made
optional in prior extensions, but the checks in our code-base do not
reflect that, assuming that it is only available in Armv8.5-A or later.

This change introduces the `ENABLE_FEAT_SB` definition, which derives
support for the `sb` instruction in the assembler from the feature
flags passed to it. Note that we assume that if this feature is enabled
then all the cores in the system support it - enabling speculation
barriers for only a subset of the cores is unsupported.

Signed-off-by: Chris Kay <chris.kay@arm.com>
Change-Id: I978ed38829385b221b10ba56d49b78f4756e20ea

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Merge "tzc400: correct FAIL_CONTROL Privileged bit" into integration

mmc:prevent accessing to the released space in case of wrong usage

1.Since in mmc_init, the most of mmc_device_info passed in are temporary variables.
In order to avoid referencing the released sp

mmc:prevent accessing to the released space in case of wrong usage

1.Since in mmc_init, the most of mmc_device_info passed in are temporary variables.
In order to avoid referencing the released space on the stack when maybe MISUSED,
it`s better to use global variables to store mmc_device_info in mmc.c
2.Delete redundant;

Signed-off-by: deqi.hu@siengine.com
Change-Id: I51ae90e7f878b19b4963508b3f7ec66339015ebc

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Merge changes from topic "od/ffa_spmc_pwr" into integration

* changes:
SPM: declare third cactus instance as UP SP
SPMD: lock the g_spmd_pm structure
FF-A: implement FFA_SECONDARY_EP_REGISTER

plat: xilinx: versal: Remove cortex-a53 compilation

Versal is a72 based that's why there is no reason to build low level
assemble code for a53.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

plat: xilinx: versal: Remove cortex-a53 compilation

Versal is a72 based that's why there is no reason to build low level
assemble code for a53.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: Iff9cf2582102d951825b87fd9af18e831ca717d6

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Merge changes from topic "matterhorn_elp" into integration

* changes:
plat: tc0: add matterhorn_elp_arm library to tc0
cpus: add Matterhorn ELP ARM cpu library

SPM: declare third cactus instance as UP SP

The FF-A v1.0 spec allows two configurations for the number of EC/vCPU
instantiated in a Secure Partition:
-A MultiProcessor (MP) SP instantiates as many

SPM: declare third cactus instance as UP SP

The FF-A v1.0 spec allows two configurations for the number of EC/vCPU
instantiated in a Secure Partition:
-A MultiProcessor (MP) SP instantiates as many ECs as the number of PEs.
An EC is pinned to a corresponding physical CPU.
-An UniProcessor (UP) SP instantiates a single EC. The EC is migrated to
the physical CPU from which the FF-A call is originating.
This change permits exercising the latter case within the TF-A-tests
framework.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I7fae0e7b873f349b34e57de5cea496210123aea0

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SPMD: lock the g_spmd_pm structure

Add a lock and spin lock/unlock calls when accessing the fields of the
SPMD PM structure.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I9bab7

SPMD: lock the g_spmd_pm structure

Add a lock and spin lock/unlock calls when accessing the fields of the
SPMD PM structure.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I9bab705564dc1ba003c29512b1f9be5f126fbb0d

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FF-A: implement FFA_SECONDARY_EP_REGISTER

Remove the former impdef SPMD service for SPMC entry point
registration. Replace with FFA_SECONDARY_EP_REGISTER ABI
providing a single entry point address i

FF-A: implement FFA_SECONDARY_EP_REGISTER

Remove the former impdef SPMD service for SPMC entry point
registration. Replace with FFA_SECONDARY_EP_REGISTER ABI
providing a single entry point address into the SPMC for
primary and secondary cold boot.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I067adeec25fc12cdae90c15a616903b4ac4d4d83

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Merge changes from topic "linux_as_bl33" into integration

* changes:
plat/arm: Remove ARM_LINUX_KERNEL_AS_BL33 relying on RESET_TO_BL31
plat/arm: Always allow ARM_LINUX_KERNEL_AS_BL33

doc: update maintainer list for Arm platforms

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I24a1697d0e0ec9289d272f0e96a252894faf12ef

doc: re-format maintainer.rst file rendering

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I9fafeb966eeec35527647282b953d88f6aa383be

plat: tc0: add matterhorn_elp_arm library to tc0

Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: Ie199c60553477c43d1665548ae78cdfd1aa7ffcf

cpus: add Matterhorn ELP ARM cpu library

Change-Id: Ie1acde619a5b21e09717c0e80befb6d53fd16607
Signed-off-by: Usama Arif <usama.arif@arm.com>

Merge changes I9c9ed516,I2788eaf6 into integration

* changes:
qemu/qemu_sbsa: fix memory type of secure NOR flash
qemu/qemu_sbsa: spm_mm supports 512 cores

Merge "plat: xilinx: zynqmp: Add missing ids for 43/46/47dr devices" into integration

driver: brcm: add USB driver

Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com>
Change-Id: I456aa7a641fffa8ea4e833615af3effec42a31b2

Merge "plat/rockchip: Use common gicv2.mk" into integration

plat/rockchip: Use common gicv2.mk

Compiling BL31 for the Rockchip platform now produces a message about
the deprecation of gic_common.c.
Follow the advice and use include gicv2.mk instead.

Signed-

plat/rockchip: Use common gicv2.mk

Compiling BL31 for the Rockchip platform now produces a message about
the deprecation of gic_common.c.
Follow the advice and use include gicv2.mk instead.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Change-Id: I396b977d57975dba27cfed801ad5264bbbde2b5e

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Merge "mediatek: mt8192: fix MISSING_BREAK" into integration

tzc400: correct FAIL_CONTROL Privileged bit

When bit 20 of TZC400 Fail control register [1] is set to 1, it means
Privileged access, the macros FAIL_CONTROL_PRIV_PRIV and
FAIL_CONTROL_PRIV_UNPRIV ar

tzc400: correct FAIL_CONTROL Privileged bit

When bit 20 of TZC400 Fail control register [1] is set to 1, it means
Privileged access, the macros FAIL_CONTROL_PRIV_PRIV and
FAIL_CONTROL_PRIV_UNPRIV are then updated to reflect this.

[1] https://developer.arm.com/documentation/ddi0504/c/programmers-model/register-descriptions/fail-control-register?lang=en

Change-Id: I01e522fded5cf66c9827293ddcf543c79f9e509e
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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mediatek: mt8192: fix MISSING_BREAK

The case for value "VCOREFS_SMC_CMD_INIT" is not
terminated by a "break" statement.

Signed-off-by: Roger Lu <roger.lu@mediatek.com>
Change-Id: I56cc7c1648e101c0d

mediatek: mt8192: fix MISSING_BREAK

The case for value "VCOREFS_SMC_CMD_INIT" is not
terminated by a "break" statement.

Signed-off-by: Roger Lu <roger.lu@mediatek.com>
Change-Id: I56cc7c1648e101c0da6e77e592e6edbd5d37724e

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Merge "SDEI: updata the affinity of shared event" into integration

SDEI: updata the affinity of shared event

when updata routing of an SDEI event, if the registration flags
is SDEI_REGF_RM_PE, need to updata the affinity of shared event.

Signed-off-by: Tony Xie <t

SDEI: updata the affinity of shared event

when updata routing of an SDEI event, if the registration flags
is SDEI_REGF_RM_PE, need to updata the affinity of shared event.

Signed-off-by: Tony Xie <tony.xie@rock-chips.com>
Change-Id: Ie5d7cc4199253f6af1c28b407f712caac3092d06

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Merge changes I76eee5c5,Ie45ab1d8,Iddcb83d3,I4425777d,I5be2837c, ... into integration

* changes:
drivers/gicv3: also shift eSPI register offset in GICD_OFFSET_64()
drivers/gicv3: add debug log f

Merge changes I76eee5c5,Ie45ab1d8,Iddcb83d3,I4425777d,I5be2837c, ... into integration

* changes:
drivers/gicv3: also shift eSPI register offset in GICD_OFFSET_64()
drivers/gicv3: add debug log for maximum INTID of SPI and eSPI
drivers/gicv3: limit SPI ID to avoid misjudgement in GICD_OFFSET()
drivers/gicv3: fix logical issue for num_eints
drivers/gicv3: fix potential GICD context override with ESPI enabled
drivers/gicv3: use mpidr to probe GICR for current CPU

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