Merge "fix(plat/mediatek/me8195): fix error setting for SPM" into integration

Merge changes from topic "fwu-refactor" into integration

* changes:
refactor(plat/arm): use mmio* functions to read/write NVFLAGS registers
refactor(plat/arm): mark the flash region as read-only

Merge changes from topic "fwu-refactor" into integration

* changes:
refactor(plat/arm): use mmio* functions to read/write NVFLAGS registers
refactor(plat/arm): mark the flash region as read-only
refactor(plat/arm): update NV flags on image load/authentication failure

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Merge changes from topic "marvell-a3k-a8k-updates" into integration

* changes:
fix(plat/marvell/a3k): Fix building uart-images.tgz.bin archive
refactor(plat/marvell/a3k): Rename *_CFG and *_SIG

Merge changes from topic "marvell-a3k-a8k-updates" into integration

* changes:
fix(plat/marvell/a3k): Fix building uart-images.tgz.bin archive
refactor(plat/marvell/a3k): Rename *_CFG and *_SIG variables
refactor(plat/marvell/a3k): Rename DOIMAGETOOL to TBB
refactor(plat/marvell/a3k): Remove useless DOIMAGEPATH variable
fix(plat/marvell/a3k): Fix check for external dependences
fix(plat/marvell/a8k): Add missing build dependency for BLE target
fix(plat/marvell/a8k): Correctly set include directories for individual targets
fix(plat/marvell/a8k): Require that MV_DDR_PATH is correctly set

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fix(plat/mediatek/me8195): fix error setting for SPM

There is a error setting for SPM, so we need to fix this issue.

Signed-off-by: Garmin Chang <garmin.chang@mediatek.com>
Change-Id: I741a5dc1505a

fix(plat/mediatek/me8195): fix error setting for SPM

There is a error setting for SPM, so we need to fix this issue.

Signed-off-by: Garmin Chang <garmin.chang@mediatek.com>
Change-Id: I741a5dc1505a831fe48fd5bc3da9904db14c8a57

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Merge "errata: workaround for Neoverse V1 errata 1940577" into integration

errata: workaround for Neoverse V1 errata 1940577

Neoverse V1 erratum 1940577 is a Cat B erratum, present in some
revisions of the V1 processor core. The workaround is to insert a
DMB ST before acq

errata: workaround for Neoverse V1 errata 1940577

Neoverse V1 erratum 1940577 is a Cat B erratum, present in some
revisions of the V1 processor core. The workaround is to insert a
DMB ST before acquire atomic instructions without release semantics.
This issue is present in revisions r0p0 - r1p1 but this workaround
only applies to revisions r1p0 - r1p1, there is no workaround for older
versions.

SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I210ad7d8f31c81b6ac51b028dfbce75a725c11aa

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fix(rk3399/suspend): correct LPDDR4 resume sequence

This change adds 208 bytes to PMUSRAM, pushing the end of text from
0xff3b0de0 to 0xff3b0eb0, which is still shy of the maximum
0xff3b1000.

Furth

fix(rk3399/suspend): correct LPDDR4 resume sequence

This change adds 208 bytes to PMUSRAM, pushing the end of text from
0xff3b0de0 to 0xff3b0eb0, which is still shy of the maximum
0xff3b1000.

Further, this skips enabling the watchdog when it's not being used
elsewhere, as you can't turn the watchdog off.

Change-Id: I2e6fa3c7e01f2be6b32ce04ce479edf64e278554
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

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Merge changes Iebb86a0b,I7fe63311 into integration

* changes:
refactor(plat/nxp/lx216x): refine variable definition
refactor(plat/nxp/lx216x): use common make variables

Merge changes I2b3aa9bd,I3237199b into integration

* changes:
docs: add mt6795 to deprecated list
feat(plat/mediatek/mt8195): add DCM driver

Merge "errata: workaround for Neoverse V1 errata 1791573" into integration

Merge "fix(plat/marvell/a3k): fix printing info messages on output" into integration

Merge "fix(rockchip/rk3399): fix dram section placement" into integration

docs: add mt6795 to deprecated list

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I2b3aa9bd0c23c360ecee673c68e1b2c92bc6d2be

errata: workaround for Neoverse V1 errata 1791573

Neoverse V1 erratum 1791573 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.

SDEN can be found here:
http

errata: workaround for Neoverse V1 errata 1791573

Neoverse V1 erratum 1791573 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.

SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ic6f92da4d0b995bd04ca5b1673ffeedaebb71d10

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fix(plat/marvell/a3k): fix printing info messages on output

INFO() macro for every call prepends "INFO: " string. Therefore
current code prints unreadable debug messages:

"INFO: set_io_add

fix(plat/marvell/a3k): fix printing info messages on output

INFO() macro for every call prepends "INFO: " string. Therefore
current code prints unreadable debug messages:

"INFO: set_io_addr_dec 0 result: ctrl(0x3fff3d01) base(0x0)INFO: "
"INFO: Set IO decode window successfully, base(0xc000)INFO: win_attr(3d) max_dram_win(2) max_remap(0)INFO: win_offset(8)"

Fix it by calling exactly one INFO() call for one line. After this
change output is:

"INFO: set_io_addr_dec 0 result: ctrl(0x3fff3d01) base(0x0) remap(0x0)"
"INFO: Set IO decode window successfully, base(0xc000) win_attr(3d) max_dram_win(2) max_remap(0) win_offset(8)"

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I6084e64c6f4da6c1929e5300588e4ba2608ca745

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Merge "docs(maintainers): add Julius Werner as Rockchip platform code owner" into integration

fix(drivers/scmi-msg): smt: fix build for aarch64

For AARCH64, BIT() will make the number as ULL type, let use BIT_32()
here.

And use %zu for size_t print format.

Reviewed-by: Jacky Bai <ping.bai@

fix(drivers/scmi-msg): smt: fix build for aarch64

For AARCH64, BIT() will make the number as ULL type, let use BIT_32()
here.

And use %zu for size_t print format.

Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I1dc18d374cd2c6eb83b40b66ed6189dcc6a21728

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feat(io_mtd): offset management for FIP usage

A new seek handler is also created. It will be used for NAND to add an
extra offset in case of bad blocks, when FIP is used.

Change-Id: I03fb1588b44029

feat(io_mtd): offset management for FIP usage

A new seek handler is also created. It will be used for NAND to add an
extra offset in case of bad blocks, when FIP is used.

Change-Id: I03fb1588b44029db50583c0b2e7af7a1e88a5a7a
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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feat(nand): count bad blocks before a given offset

In case of FIP, the offsets given in the FIP header are relative.
If bad blocks are found between the FIP base address and this offset,
the offset

feat(nand): count bad blocks before a given offset

In case of FIP, the offsets given in the FIP header are relative.
If bad blocks are found between the FIP base address and this offset,
the offset should be updated, taking care of the bad blocks.

Change-Id: I96fefabb583b3d030ab05191bae7d45cfeefe341
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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feat(plat/st): add helper to save boot interface

Some parameters from BootROM boot context can be required after boot.
To save space in SYSRAM, this context can be overwritten during images
load seq

feat(plat/st): add helper to save boot interface

Some parameters from BootROM boot context can be required after boot.
To save space in SYSRAM, this context can be overwritten during images
load sequence. The needed information (here the boot interface) is
then saved in a local variable.

Change-Id: I5e1ad4630ccf78480f415a0a83939005ae67729e
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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fix(plat/st): improve DDR get size function

Avoid parsing device tree every time when returning
the DDR size.
A cache flush on this size is also added because TZC400 configuration
is applied at the

fix(plat/st): improve DDR get size function

Avoid parsing device tree every time when returning
the DDR size.
A cache flush on this size is also added because TZC400 configuration
is applied at the end of BL2 after MMU and data cache being turned off.
Configuration needs to retrieve the DDR size to generate the correct
region. Access to the size fails because the value is still in the data
cache. Flushing the size is mandatory.

Change-Id: I3dd1958f37d806f9c15a5d4151968935f6fe642e
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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refactor(plat/st): map DDR secure at boot

In BL2, the DDR can be mapped as secured in MMU, as no other SW
has access to it during its execution.
The TZC400 configuration is also updated to reflect t

refactor(plat/st): map DDR secure at boot

In BL2, the DDR can be mapped as secured in MMU, as no other SW
has access to it during its execution.
The TZC400 configuration is also updated to reflect this. When using
OP-TEE, the TZC400 is reconfigured at the end of BL2, to match OP-TEE
mapping. Else, SP_min will be in charge to reconfigure TZC400 to set
DDR non-secure.

Change-Id: Ic5ec614b218f733796feeab1cdc425d28cc7c103
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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refactor(plat/st): rework TZC400 configuration

Add new static functions to factorize code in stm32mp1_security.c.

Change-Id: Ifa5a1aaf7c56c25dba9a0ab8e985496d7cb06990
Signed-off-by: Yann Gautier <y

refactor(plat/st): rework TZC400 configuration

Add new static functions to factorize code in stm32mp1_security.c.

Change-Id: Ifa5a1aaf7c56c25dba9a0ab8e985496d7cb06990
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Merge "docs: update supported FVP models as per release 11.15.14" into integration

Merge "refactor(mpam): remove unused function declaration" into integration