Merge "feat(ff-a): adding notifications SMC IDs" into integration

Merge changes I9c7cc586,I48ee254a,I9f65c6af,I5872d95b,I2dbbdcb4, ... into integration

* changes:
feat(docs/nxp/layerscape): add ls1028a soc and board support
feat(plat/nxp/ls1028ardb): add ls102

Merge changes I9c7cc586,I48ee254a,I9f65c6af,I5872d95b,I2dbbdcb4, ... into integration

* changes:
feat(docs/nxp/layerscape): add ls1028a soc and board support
feat(plat/nxp/ls1028ardb): add ls1028ardb board support
feat(plat/nxp/ls1028a): add ls1028a soc support
feat(plat/nxp/common): define default SD buffer
feat(driver/nxp/xspi): add MT35XU02G flash info
feat(plat/nxp/common): add SecMon register definition for ch_3_2
feat(driver/nxp/dcfg): define RSTCR_RESET_REQ
feat(plat/nxp/common/psci): define CPUECTLR_TIMER_2TICKS
feat(plat/nxp/common): define default PSCI features if not defined
feat(plat/nxp/common): define common macro for ARM registers
feat(plat/nxp/common): add CCI and EPU address definition

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errata: workaround for Cortex-A710 erratum 2083908

Cortex-A710 erratum 2083908 is a Cat B erratum that applies to
revision r2p0 and is still open. The workaround is to set
CPUACTLR5_EL1[13] to 1.

S

errata: workaround for Cortex-A710 erratum 2083908

Cortex-A710 erratum 2083908 is a Cat B erratum that applies to
revision r2p0 and is still open. The workaround is to set
CPUACTLR5_EL1[13] to 1.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I876d26a7ac6ab0d7c567a9ec9f34fc0f952589d8

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Merge "fix(plat/mediatek/mt8195): fix coverity fail" into integration

refactor(drivers/marvell/comphy-3700): simplify usage of sata power off

Function mvebu_a3700_comphy_sata_power_off() uses comphy_mode parameter
only for extracting mode bits. Mode is always COMPHY_S

refactor(drivers/marvell/comphy-3700): simplify usage of sata power off

Function mvebu_a3700_comphy_sata_power_off() uses comphy_mode parameter
only for extracting mode bits. Mode is always COMPHY_SATA_MODE, so
there is no need to pass comphy_mode parameter to this function. Use
directly COMPHY_SATA_MODE in mvebu_a3700_comphy_sata_power_off().

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ib6b7c2bf62c1ef4d8a6af240c08696d5cd506b14

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Merge "refactor(spmd): boot interface and pass core id" into integration

feat(docs/nxp/layerscape): add ls1028a soc and board support

Update nxp-layerscape to add ls1028a SoC and ls1028ardb board
support.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I9c7cc5

feat(docs/nxp/layerscape): add ls1028a soc and board support

Update nxp-layerscape to add ls1028a SoC and ls1028ardb board
support.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I9c7cc586f3718b488a6757994d65f6df69e7e165

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feat(plat/nxp/ls1028ardb): add ls1028ardb board support

The LS1028A reference design board (RDB) is a computing,
evaluation, and development platform that supports industrial
IoT applications, human

feat(plat/nxp/ls1028ardb): add ls1028ardb board support

The LS1028A reference design board (RDB) is a computing,
evaluation, and development platform that supports industrial
IoT applications, human machine interface solutions, and
industrial networking.

It supports the following features:
1. Layerscape LS1028A dual-core processor based on Cortex-A72
at 1.3 GHz.
2. 4 GB DDR4 SDRAM w/ECC
3. Support Ethernet:
1) x1 RJ45 connector for 1Gbps Ethernet support w/TSN, 1588
2) x4 RJ45 connector for 1Gbps Ethernet switch support w/TSN,
1588 (QSGMII)
3. With Basic Peripherals and Interconnect
2x M.2 Type E slots with PCIe Gen 3.0 x1
1x M.2 Type B slot with SATA 3.0 (resistor mux with 1 Type E slot)
1x Type A USB 3.0 super-speed port
1x Type C USB 3.0 super-speed port
1x DisplayPort interface
2x DB9 RS232 serial ports
2x DB9 CAN interfaces
1x 3.5 mm audio out
2x MikroBUS™ sockets

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: York Sun <york.sun@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Change-Id: I48ee254a488ae4af227641da3875a1e9a63a720c

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feat(plat/nxp/ls1028a): add ls1028a soc support

The QorIQ LS1028A processor integrates two 64-bit ARM Cortex-A72
cores with a GPU and LCD controller, as well as a TSNenabled
Ethernet port and a TSN-

feat(plat/nxp/ls1028a): add ls1028a soc support

The QorIQ LS1028A processor integrates two 64-bit ARM Cortex-A72
cores with a GPU and LCD controller, as well as a TSNenabled
Ethernet port and a TSN-enabled switch with four external ports.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Change-Id: I9f65c6af5db7e20702828cd208290c1b43a54941

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refactor(drivers/st/clk): change fdt_get_rcc_node as static

Change the fdt_get_rcc_node function to static, as it is used only in
stm32mp_clkfunc.c file; it is only a cleanup change without function

refactor(drivers/st/clk): change fdt_get_rcc_node as static

Change the fdt_get_rcc_node function to static, as it is used only in
stm32mp_clkfunc.c file; it is only a cleanup change without functional
modification.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: Ib4ef110f6f1b16dbaa727a065e40275d3cf58a73

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Merge changes I48d23785,I3dd99d87 into integration

* changes:
docs(maintainers): update qti maintainer
feat(plat/qti/sc7280): support for qti sc7280 plat

docs(maintainers): update qti maintainer

Add lachit and Sreevyshanavi in qti maintainer

Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
Change-Id: I48d2378551775a3ad63bc7c3a4e2b62b15c4770d

feat(plat/qti/sc7280): support for qti sc7280 plat

new qti platform sc7280 support addition

Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
Change-Id: I3dd99d8744a6c313f7dfbbee7ae2cbd6f216

feat(plat/qti/sc7280): support for qti sc7280 plat

new qti platform sc7280 support addition

Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
Change-Id: I3dd99d8744a6c313f7dfbbee7ae2cbd6f21656c1

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fix(stm32_console): do not skip init for crash console

In BL32, only skip UART initialization if UART enable bit is set.
Due to patch [1], a reset of UART is done in crash console init.
In this case

fix(stm32_console): do not skip init for crash console

In BL32, only skip UART initialization if UART enable bit is set.
Due to patch [1], a reset of UART is done in crash console init.
In this case, UART should then be reconfigured.

[1] 7fa2e96e1 ("stm32mp1: add UART reset in crash console init")

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I650d4c387b60dd74b780e6f3adfd629ea44f5834

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fix(plat/st): add UART reset in crash console init

Add the reset set/clear sequence at the beginning of the function
plat_crash_console_init(). If not done, there is a risk that the UART
is in a bad

fix(plat/st): add UART reset in crash console init

Add the reset set/clear sequence at the beginning of the function
plat_crash_console_init(). If not done, there is a risk that the UART
is in a bad state and will not be able to print correct characters.

Change-Id: Id31e28773d6c4f26f16d3569d1e3c5aa0e26e039
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Merge "fix(drivers/tzc400): never disable filter 0" into integration

refactor(stm32mp1_clk): update RCC registers file

The file is first generated with the peripheral spirit XML file.
And then we add some common definition, to ease driver development.

Change-Id: I4c

refactor(stm32mp1_clk): update RCC registers file

The file is first generated with the peripheral spirit XML file.
And then we add some common definition, to ease driver development.

Change-Id: I4c222cf006caf27cda6da044eaf184ce66bb1442
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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fix(stm32mp1_clk): keep RTCAPB clock always on

Further information such as boot instance are sent over backup
registers. In order to guarantee direct access to backup registers
in uboot, we will kee

fix(stm32mp1_clk): keep RTCAPB clock always on

Further information such as boot instance are sent over backup
registers. In order to guarantee direct access to backup registers
in uboot, we will keep the RTC clock enabled.

Change-Id: I16572d422bfebbf39190a87db8046df486ce91c8
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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fix(stm32mp1_clk): fix RTC clock rating

When RTC clock source is HSE, the RTCDIV is not taken into account.

Change-Id: I1613b638e8932c03f3349adb01e13f5294a3bf5d
Signed-off-by: Gabriel Fernandez <ga

fix(stm32mp1_clk): fix RTC clock rating

When RTC clock source is HSE, the RTCDIV is not taken into account.

Change-Id: I1613b638e8932c03f3349adb01e13f5294a3bf5d
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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fix(stm32mp1_clk): correctly manage RTC clock source

The clksrc value contains the RCC register address and the clock
source number. When applying the clock source, we should filter out
the RCC regi

fix(stm32mp1_clk): correctly manage RTC clock source

The clksrc value contains the RCC register address and the clock
source number. When applying the clock source, we should filter out
the RCC register address from the given value.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I4345b03de7b9afd1df78df4131431cf1eb43ec17

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fix(spi_nand): check correct manufacturer id

On most of SPI NAND, the read id command needs a dummy byte,
except GIGADEVICE SPI NAND that needs an address.
To be compliant with all memories provider

fix(spi_nand): check correct manufacturer id

On most of SPI NAND, the read id command needs a dummy byte,
except GIGADEVICE SPI NAND that needs an address.
To be compliant with all memories providers, the first byte returns
by the READ_ID command is not relevant (garbage).

Change-Id: Ife74ccab333dd1a04799abe230d3f07fa6ea1edb
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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fix(spi_nand): check that parameters have been set

This patch checks that the SPI NAND parameters needed by
the framework have been set before starting to read data.

Change-Id: I17b36606701c44864dc

fix(spi_nand): check that parameters have been set

This patch checks that the SPI NAND parameters needed by
the framework have been set before starting to read data.

Change-Id: I17b36606701c44864dcf1783f810da5c8cbf88f2
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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Merge changes from topic "TrcDbgExt" into integration

* changes:
feat(plat/fvp): enable trace extension features by default
feat(trf): enable trace filter control register access from lower NS E

Merge changes from topic "TrcDbgExt" into integration

* changes:
feat(plat/fvp): enable trace extension features by default
feat(trf): enable trace filter control register access from lower NS EL
feat(trf): initialize trap settings of trace filter control registers access
feat(sys_reg_trace): enable trace system registers access from lower NS ELs
feat(sys_reg_trace): initialize trap settings of trace system registers access
feat(trbe): enable access to trace buffer control registers from lower NS EL
feat(trbe): initialize trap settings of trace buffer control registers access

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fix(plat/mediatek/mt8195): fix coverity fail

Add break to correct the driver flow.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ie20f402d543fbf90172671e007fad30d5dc2ab10

feat(ff-a): adding notifications SMC IDs

Defining SMC IDs for FF-A v1.1 notifications functionality, and adding
them to SPMD SMC handler, to ensure calls are forwarded to the SPMC.

Signed-off-by: J

feat(ff-a): adding notifications SMC IDs

Defining SMC IDs for FF-A v1.1 notifications functionality, and adding
them to SPMD SMC handler, to ensure calls are forwarded to the SPMC.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: Icc88aded0fd33507f7795e996bd4ff1c2fe679c8

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