Merge "fix(gicv3): fix iroute value wrong issue" into integration

Merge changes from topic "st_uart" into integration

* changes:
feat(plat/st): add STM32MP_UART_PROGRAMMER target
feat(plat/st): add STM32CubeProgrammer support on UART
feat(drivers/st/uart): a

Merge changes from topic "st_uart" into integration

* changes:
feat(plat/st): add STM32MP_UART_PROGRAMMER target
feat(plat/st): add STM32CubeProgrammer support on UART
feat(drivers/st/uart): add uart driver for STM32MP1

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Merge "fix(xlat): fix bug on VERBOSE trace" into integration

Merge "docs: mark STM32MP_USE_STM32IMAGE as deprecated" into integration

docs: mark STM32MP_USE_STM32IMAGE as deprecated

This macro was used for the legacy boot mode on SPM32MP platforms.
The recommended boot method is now FIP.
The code under this macro will be removed a

docs: mark STM32MP_USE_STM32IMAGE as deprecated

This macro was used for the legacy boot mode on SPM32MP platforms.
The recommended boot method is now FIP.
The code under this macro will be removed after tag v2.7.

Change-Id: Id3b7baea2d3e6ea8b36a4cd0b107cb92591a172b
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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fix(gicv3): fix iroute value wrong issue

As mpidr is unsigned long long, U should be ULL. We use macro to
fix this issue.

Signed-off-by: Ming Huang <huangming@linux.alibaba.com>
Change-Id: I7dfd51a

fix(gicv3): fix iroute value wrong issue

As mpidr is unsigned long long, U should be ULL. We use macro to
fix this issue.

Signed-off-by: Ming Huang <huangming@linux.alibaba.com>
Change-Id: I7dfd51a63f27f471794bcbf72ffff0c1a0598b46

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Merge changes I7c9f8490,Ia92c6d19 into integration

* changes:
feat(plat/mediatek/mt8195): add EMI MPU surppot for SCP and DSP
feat(plat/mediatek/mt8195): dump EMI MPU configurations

feat(plat/mediatek/mt8195): add EMI MPU surppot for SCP and DSP

1. Enable domain D0 and D3 (SCP) access 0x50000000~0x51400000.
2. Enable domain D4 (DSP & AFE) access 0x60000000~0x610FFFFF.

BUG=b:20

feat(plat/mediatek/mt8195): add EMI MPU surppot for SCP and DSP

1. Enable domain D0 and D3 (SCP) access 0x50000000~0x51400000.
2. Enable domain D4 (DSP & AFE) access 0x60000000~0x610FFFFF.

BUG=b:204347737
TEST=build pass

Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
Change-Id: I7c9f8490b8898008ba6844c34c9e80caa6066cbc

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feat(plat/mediatek/mt8195): dump EMI MPU configurations

Add dump_emi_mpu_regions() to dump EMI MPU configurations.

BUG=b:204347737
TEST=build pass

Change-Id: Ia92c6d19b96d429682dff1680d5f5b2dc2bc1

feat(plat/mediatek/mt8195): dump EMI MPU configurations

Add dump_emi_mpu_regions() to dump EMI MPU configurations.

BUG=b:204347737
TEST=build pass

Change-Id: Ia92c6d19b96d429682dff1680d5f5b2dc2bc1b8f
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>

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Merge "fix(plat/arm/sgi): disable SVE for NS to support SPM_MM builds" into integration

fix(xlat): fix bug on VERBOSE trace

When log level is set to VERBOSE, a build error
happens due a incorrect format stringon a printf
call.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobri

fix(xlat): fix bug on VERBOSE trace

When log level is set to VERBOSE, a build error
happens due a incorrect format stringon a printf
call.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I8f869e078a3c179470977dadc063521c1ae30dbb

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feat(plat/st): add STM32MP_UART_PROGRAMMER target

Handle boot from UART with STM32CubeProgammer based on mmap io
for STM32MP15.

Depends-On: Iba84e8dfd67b9f30416efb0f6778e48ba1f75dad
Signed-off-by:

feat(plat/st): add STM32MP_UART_PROGRAMMER target

Handle boot from UART with STM32CubeProgammer based on mmap io
for STM32MP15.

Depends-On: Iba84e8dfd67b9f30416efb0f6778e48ba1f75dad
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: Ibd719dd46a11da78633728675ef6639635b6cf67

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feat(plat/st): add STM32CubeProgrammer support on UART

Add a file to support the STMicroelectronics tool STM32CubeProgrammer
over UART in BL2 for STM32MP15x platform.

This tools is based on protoco

feat(plat/st): add STM32CubeProgrammer support on UART

Add a file to support the STMicroelectronics tool STM32CubeProgrammer
over UART in BL2 for STM32MP15x platform.

This tools is based on protocol defined in AN5275,
"USB DFU/USART protocols used in STM32MP1 Series bootloaders"
based on STM32 MCU protocols (AN3155, "USART protocol used
in the STM32 bootloader").

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: I956c95d8de0a94d1eb8e61f043651dae7b838170

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feat(drivers/st/uart): add uart driver for STM32MP1

Add a UART/USART driver for STM32 with complete a hardware support;
it used for STM32CubeProgrammer support with even parity.

This driver is not

feat(drivers/st/uart): add uart driver for STM32MP1

Add a UART/USART driver for STM32 with complete a hardware support;
it used for STM32CubeProgrammer support with even parity.

This driver is not used for console, which is already handle
by a simple driver (drivers/st/uart/aarch32/stm32_console.S).

Change-Id: Ia9266e5d177fe7fd09c8a15b81da1a05b1bc8b2d
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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feat(stm32mp1): preserve the PLL4 settings for USB boot

The PLL4 can be used by ROM code as the source clock of USB PHYC and,
in this case, the PLL4 configuration must be preserved
with pll4_preserv

feat(stm32mp1): preserve the PLL4 settings for USB boot

The PLL4 can be used by ROM code as the source clock of USB PHYC and,
in this case, the PLL4 configuration must be preserved
with pll4_preserve to avoid USB disturbance.

This patch also adds an error when the clock tree PLL4 configuration
is not the PLL4 configuration used by ROM code; this error allows to
detect a invalid clock tree.

This commit corrects the coverity issue 343023.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: I4bae9312a2db8dd342a38e649513d689b13976bb

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Merge changes I8990bce2,Iacef5e67,I2976c0a4,I8551a802 into integration

* changes:
fix(plat/marvell/a3720/uart): do external reset during initialization
feat(plat/marvell/a3k): add north and sout

Merge changes I8990bce2,Iacef5e67,I2976c0a4,I8551a802 into integration

* changes:
fix(plat/marvell/a3720/uart): do external reset during initialization
feat(plat/marvell/a3k): add north and south bridge reset registers
fix(plat/marvell/a3720/uart): configure UART after TX FIFO reset
feat(plat/marvell/a3720/uart): preserve x1/x2 regs in console_a3700_core_init()

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fix(plat/marvell/a3720/uart): do external reset during initialization

Sometimes when changing UART clock from TBG to XTAL, UART HW enters into
some broken state. It does not transit characters from

fix(plat/marvell/a3720/uart): do external reset during initialization

Sometimes when changing UART clock from TBG to XTAL, UART HW enters into
some broken state. It does not transit characters from TX FIFO anymore
and TX FIFO stays always empty. TX FIFO reset does not recover UART HW
from this broken state.

Experiments show that external reset can fix UART HW from this broken
state.

TF-A fatal error handler calls console_a3700_core_init() function to
initialize UART HW. This handler may be called anytime during CPU
runtime, also when kernel is running.

U-Boot or Linux kernel may change UART clock to TBG to achieve higher
baudrates. During initialization, console_a3700_core_init() resets UART
configuration to default settings, which means that it also changes
UART clock from TBG to XTAL.

Do an external reset of UART via North Bridge Peripheral reset register
to prevent this UART hangup.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I8990bce24d1a6fd8ccc47a2cd0a5ff932fcfcf14

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feat(plat/marvell/a3k): add north and south bridge reset registers

These registers make it is possible to do external resets of A3700
peripherals. Most peripherals are reset by clearing a particular

feat(plat/marvell/a3k): add north and south bridge reset registers

These registers make it is possible to do external resets of A3700
peripherals. Most peripherals are reset by clearing a particular bit,
but some need setting the bit. Reflect this via "_N" suffix in macro
names.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Iacef5e671746b831b5beea9e4fdcc59d8de84edc

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fix(plat/marvell/a3720/uart): configure UART after TX FIFO reset

If TX FIFO is not empty, do not touch UART settings and let UART HW
transmit remaining bytes from TX FIFO. New UART settings are then

fix(plat/marvell/a3720/uart): configure UART after TX FIFO reset

If TX FIFO is not empty, do not touch UART settings and let UART HW
transmit remaining bytes from TX FIFO. New UART settings are then set
only after TX FIFO is reset.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I2976c0a4fbb841d3a79d42ef67c06e70174afc3b

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feat(plat/marvell/a3720/uart): preserve x1/x2 regs in console_a3700_core_init()

Followup changes will need function arguments in registers x0, x1 and
x2. Do not modify x1 and x2 registers and instea

feat(plat/marvell/a3720/uart): preserve x1/x2 regs in console_a3700_core_init()

Followup changes will need function arguments in registers x0, x1 and
x2. Do not modify x1 and x2 registers and instead use scratch x3 and x4
registers for storing local variables.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I8551a802995f39128d2f4a8f8076b5bf463d0db0

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fix(plat/arm/sgi): disable SVE for NS to support SPM_MM builds

Commit 4333f95 ("fix(spm_mm): do not compile if SVE/SME is enabled")
introduced a comiple time check to verify if ENABLE_SVE_FOR_NS is

fix(plat/arm/sgi): disable SVE for NS to support SPM_MM builds

Commit 4333f95 ("fix(spm_mm): do not compile if SVE/SME is enabled")
introduced a comiple time check to verify if ENABLE_SVE_FOR_NS is set to
0 when SPM_MM build is enabled. To support SPM_MM builds on SGI/RD
platforms set ENABLE_SVE_FOR_NS to 0.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: If78ed7567f6d988795b2bc7f772a883783246964

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Merge changes Ia0d13c3c,I8cf821a4,I1e6a598b,I9c6dd8db,Iaf6db75e, ... into integration

* changes:
fix(plat/xilinx/versal): resolve misra R10.6
fix(plat/xilinx/versal): resolve misra R14.4
fix(p

Merge changes Ia0d13c3c,I8cf821a4,I1e6a598b,I9c6dd8db,Iaf6db75e, ... into integration

* changes:
fix(plat/xilinx/versal): resolve misra R10.6
fix(plat/xilinx/versal): resolve misra R14.4
fix(plat/xilinx/versal): resolve misra R17.7
fix(plat/xilinx/versal): resolve misra R10.3
fix(plat/xilinx/versal): resolve misra R7.2
fix(plat/xilinx/versal): resolve misra R15.7
fix(plat/xilinx/versal): resolve misra R15.6
fix(plat/xilinx/versal): resolve misra R10.1 in pm services
fix(plat/xilinx/versal): resolve misra R20.7 in pm services
fix(plat/xilinx/versal): resolve misra R10.3 in pm services
fix(plat/xilinx/versal): resolve misra R10.6 in pm services
fix(plat/xilinx/versal): resolve misra R16.3 in pm services
fix(plat/xilinx/versal): resolve misra R15.6 in pm services

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Merge changes from topic "fix_pie" into integration

* changes:
fix(pie): align fixup_gdt_reloc() for aarch64
fix(pie): do not skip __RW_END__ address during relocation

fix(pie): align fixup_gdt_reloc() for aarch64

Do not skip upper limit address (__RW_END__) during relocation process.
This align the code on what is done for AARCH32.

Change-Id: I236368376276c2d3aa

fix(pie): align fixup_gdt_reloc() for aarch64

Do not skip upper limit address (__RW_END__) during relocation process.
This align the code on what is done for AARCH32.

Change-Id: I236368376276c2d3aa79adce13ca49f4023ce369
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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fix(pie): do not skip __RW_END__ address during relocation

In fixup_gdt_reloc(), do not skip the last address (__RW_END__) for
dynamic relocations.
Else, the invalidation of the data done under _ini

fix(pie): do not skip __RW_END__ address during relocation

In fixup_gdt_reloc(), do not skip the last address (__RW_END__) for
dynamic relocations.
Else, the invalidation of the data done under _init_c_runtime in
el3_entrypoint_common macro will not be correct.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I1166a59ac964ec8ad4e099cb3600e843afc71d82

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