Merge "fix(lib): align round_up with MISRA 10.1 and 10.8" into integration

Merge changes from topic "ar/v2_errata" into integration

* changes:
fix(cpus): workaround for Neoverse-V2 erratum 3701771
fix(cpus): workaround for Neoverse-V2 erratum 3841324

Merge "fix(rcar3): add missing image_base/size assignment to BL33 image loading path" into integration

Merge "fix(intel): undo setting USB 3.1 reset pulse bit in BL2" into integration

Merge "fix(intel): update the AES GCM/GCM_GHASH modes return data size" into integration

Merge "fix(intel): configure SCR1 for 32/16 non-secure SMRs and context banks" into integration

Merge "fix(arm): don't override the gic redistributor frames" into integration

Merge "fix: remove unused cpu_data related macros" into integration

build(dev-deps): bump pyright

Bumps the dev-deps group with 1 update in the /tools/memory directory: [pyright](https://github.com/RobertCraigie/pyright-python).

Updates `pyright` from 1.1.405 to 1.

build(dev-deps): bump pyright

Bumps the dev-deps group with 1 update in the /tools/memory directory: [pyright](https://github.com/RobertCraigie/pyright-python).

Updates `pyright` from 1.1.405 to 1.1.406
- [Release notes](https://github.com/RobertCraigie/pyright-python/releases)
- [Commits](https://github.com/RobertCraigie/pyright-python/compare/v1.1.405...v1.1.406)

--
updated-dependencies:
- dependency-name: pyright
dependency-version: 1.1.406
dependency-type: direct:development
update-type: version-update:semver-patch
dependency-group: dev-deps
...

Change-Id: I13fe776cbf3c0cf2540d7c9c65d837daff273215
Signed-off-by: dependabot[bot] <support@github.com>

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fix(cpus): workaround for Neoverse-V2 erratum 3701771

Neoverse-V2 erratum 3701771 that applies to r0p0, r0p1, r0p2 is
still Open.

The workaround is for EL3 software that performs context save/resto

fix(cpus): workaround for Neoverse-V2 erratum 3701771

Neoverse-V2 erratum 3701771 that applies to r0p0, r0p1, r0p2 is
still Open.

The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.

The mitigation is implemented in commit 7455cd172 and this patch should be applied on top of it.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2332927/latest

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ic0ad68f7bd393bdc03343d5ba815adb23bf6a24d

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fix(security): fix Neoverse V2 CVE-2022-23960

Apply CVE-2022-23960 mitigation to Neoverse V2, revision r0p0 only.
Ref - https://developer.arm.com/documentation/110280/latest/

Change-Id: I859012281f

fix(security): fix Neoverse V2 CVE-2022-23960

Apply CVE-2022-23960 mitigation to Neoverse V2, revision r0p0 only.
Ref - https://developer.arm.com/documentation/110280/latest/

Change-Id: I859012281fc67243f050d27e364f27434389c0cf
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(security): fix Cortex-X3 CVE-2022-23960

Apply CVE-2022-23960 mitigation to Cortex-X3, revision r1p0 and earlier only.
Ref - https://developer.arm.com/documentation/110280/latest/

Change-Id: I3d

fix(security): fix Cortex-X3 CVE-2022-23960

Apply CVE-2022-23960 mitigation to Cortex-X3, revision r1p0 and earlier only.
Ref - https://developer.arm.com/documentation/110280/latest/

Change-Id: I3d46fa70c80129ca0085d8245ee013f11a8842e3
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(security): fix Cortex-A715 CVE-2022-23960

Apply CVE-2022-23960 mitigation to Cortex-A715, revision r1p0 and earlier only.
Ref - https://developer.arm.com/documentation/110280/latest/

Change-Id:

fix(security): fix Cortex-A715 CVE-2022-23960

Apply CVE-2022-23960 mitigation to Cortex-A715, revision r1p0 and earlier only.
Ref - https://developer.arm.com/documentation/110280/latest/

Change-Id: Ib6b704733e474824772cb27bd048b1e179d90da9
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(security): fix spectre bhb loop count for Cortex-A720

fix@c2a15217c3053117f4d39233002cb1830fa96670
based on https://developer.arm.com/documentation/110280/latest/
Spectre-BHB loop count K value

fix(security): fix spectre bhb loop count for Cortex-A720

fix@c2a15217c3053117f4d39233002cb1830fa96670
based on https://developer.arm.com/documentation/110280/latest/
Spectre-BHB loop count K value for Cortex-A720 is 38.

Change-Id: Ib6862dbed55e5ffcd0fcd58b45a88cf925c54154
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge "fix(fvp): do not unregister the console on system suspend" into integration

fix(fvp): do not unregister the console on system suspend

On PSCI SYSTEM_SUSPEND, Arm platforms will call
arm_system_pwr_domain_save() which will call arm_console_runtime_end().
Usually (eg CSS), th

fix(fvp): do not unregister the console on system suspend

On PSCI SYSTEM_SUSPEND, Arm platforms will call
arm_system_pwr_domain_save() which will call arm_console_runtime_end().
Usually (eg CSS), that's just a flush, but on FVP that also unregisters
the console. On HW_ASSISTED_COHERENCY=0 builds, this has the potential
to break and prevent any EL3 output after a SYSTEM_SUSPEND.

This happens because the calls to
console_unregister()/console_register() will overwrite the value of the
console_list variable in drivers/console/multi_console.c. They are
only called on a system level suspend. The bug happens when the core
wakes up. The console will be registered again as part of the
pwr_domain_suspend_finish() call. However, this call happens before the
data caches have been enabled in psci_do_pwrup_cache_maintenance(). As a
result, the write to console_list will not be reflected in the L2 cache
and other cores will not be able to read the new value.

The fix is to not unregister the console like other Arm platforms -
we don't need to reinitialise the console so there's nothing to do.

A nice side effect is that arm_console_runtime_end() no longer needs to
be weak.

Change-Id: Ibbdd4b22bad0d8f1dbd63c60ee0294d889a349a4
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes from topic "ahmed-azeem/introduce-rdaspen" into integration

* changes:
feat(dsu): enable PMU registers access at EL1
feat(rdaspen): add DSU to the device tree
feat(rdaspen): add

Merge changes from topic "ahmed-azeem/introduce-rdaspen" into integration

* changes:
feat(dsu): enable PMU registers access at EL1
feat(rdaspen): add DSU to the device tree
feat(rdaspen): add DSU support
docs(rdaspen): introduce rdaspen docs
feat(rdaspen): enable tbb on rd-aspen platform
feat(gicv3): add GIC-720AE model id
feat(rdaspen): add BL31 for RD-Aspen platform
feat(rdaspen): introduce Arm RD-Aspen platform

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chore(vscode): ignore noisy directories

Some directories undergo a high level of churn due to developer tooling
and contain little of use to the developer in day-to-day work. Including
them in the V

chore(vscode): ignore noisy directories

Some directories undergo a high level of churn due to developer tooling
and contain little of use to the developer in day-to-day work. Including
them in the VS Code project can cause the editor to consume significant
system resources unnecessarily.

This commit updates the Visual Studio configuration to avoid showing,
watching or searching these directories, reducing resource usage and
improving editor responsiveness.

Change-Id: Icea6362dd928719da0456ca54d87c96d14eb9fcc
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge "build(dev-deps): bump the dev-deps group across 1 directory with 2 updates" into integration

chore(changelog): add Visual Studio Code scope

Change-Id: Ia6d05504b801a9792409023b365527165fc7f997
Signed-off-by: Chris Kay <chris.kay@arm.com>

fix(cpus): workaround for Neoverse-V2 erratum 3841324

Neoverse-V2 erratum 3841324 is a Cat B erratum that applies to
r0p0 and r0p1. It is fixed in r0p2.

This erratum can be avoided by setting CPUAC

fix(cpus): workaround for Neoverse-V2 erratum 3841324

Neoverse-V2 erratum 3841324 is a Cat B erratum that applies to
r0p0 and r0p1. It is fixed in r0p2.

This erratum can be avoided by setting CPUACTLR_EL1[1]
prior to enabling MMU. This bit will disable a branch predictor
power savings feature. Disabling this power feature
results in negligible power movement and no performance impact.

SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2332927/latest

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I9b3a5266103e5000d207c7a270c65455d0646102

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Merge "fix(gpt): fix fill_l1_cont_desc() function" into integration

Merge "feat(xilinx): deprecate PM_REQ_SUSPEND EEMI API" into integration

fix(rcar3): add missing image_base/size assignment to BL33 image loading path

Align BL33 image loading behavior in BL2 with BL3x image
loading behavior. BL31/BL32 image load already assigns
bl_mem_p

fix(rcar3): add missing image_base/size assignment to BL33 image loading path

Align BL33 image loading behavior in BL2 with BL3x image
loading behavior. BL31/BL32 image load already assigns
bl_mem_params->image_info.image_base and
bl_mem_params->image_info.image_size, but this assignment
is missing for BL33 image load.

This assignment is essential after retrieving the destination
address and size via rcar_get_dest_addr_from_cert(), so that
the parameters are passed correctly to the next stage. Without
this assignment, the BL33 image might not be loaded or validated
properly.

This change is not considered a vulnerability fix, but rather
a correction to ensure consistency and completeness in the BL2
image load logic.

Fixes: 4f7e0fa38fdb ("fix(rcar3): fix load address range check")
Signed-off-by: Hieu Nguyen <hieu.nguyen.dn@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Commit message update
Change-Id: I3c7c70f7f8d64b53e8c0f5ed61c71031b99fcde0

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feat(dsu): enable PMU registers access at EL1

- Disable trapping of write accesses to DSU cluster PMU registers
at EL3 and EL2.
- Clear the SPME bit in CLUSTERPMMDCR_EL3 to prohibit PMU event
co

feat(dsu): enable PMU registers access at EL1

- Disable trapping of write accesses to DSU cluster PMU registers
at EL3 and EL2.
- Clear the SPME bit in CLUSTERPMMDCR_EL3 to prohibit PMU event
counting in the secure state.

Change-Id: If3eb6e997330ae86f45760e0e862c003861f3d66
Signed-off-by: Amr Mohamed <amr.mohamed@arm.com>

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