Merge "feat(cpus): add support for Canyon CPU" into integration

Merge "fix(arm): increase reserved DRAM1 mem for NS images" into integration

feat(versal2): add SPMD support for SPMC at S-EL1

Added support for SPMD when SPMC is running at S-EL1 on Versal Gen 2
platform. Added DTB with manifest addresses to BL32 for proper
initialization.

feat(versal2): add SPMD support for SPMC at S-EL1

Added support for SPMD when SPMC is running at S-EL1 on Versal Gen 2
platform. Added DTB with manifest addresses to BL32 for proper
initialization. Added `plat_spmd_handle_group0_interrupt` to handle
Group0 interrupts in SPMD. Added a new manifest source file compliant
with FFA 1.0 specification in which load_address and entrypoint
points to BL32 base address.

Change-Id: I518e2e799d3b86fcd67f9fee0af42503ca705488
Signed-off-by: Pranav Tilak <pranav.vinaytilak@amd.com>

show more ...

Merge "fix(arm): re-enable console by default in BL31" into integration

Merge "docs(s32g274a): update compilation instructions" into integration

docs(s32g274a): update compilation instructions

Changes to the Poetry memory module have removed
support for the `-f` option, following commit
8daebefe59e ("refactor(memmap)!: change behavioural fla

docs(s32g274a): update compilation instructions

Changes to the Poetry memory module have removed
support for the `-f` option, following commit
8daebefe59e ("refactor(memmap)!: change behavioural flags to commands").

This update replaces `-f` with `footprint` option
to ensure compatibility with the updated memory
module.

Change-Id: I58eb2c5e9ca649c7a00696b0a3b5c8e02fa29c84
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

show more ...

fix(xilinx): fix missing security flag in suspend path

Suspend flow was always programming wakeup sources with a fixed
secure flag, regardless of whether the caller was secure or
non-secure. This ma

fix(xilinx): fix missing security flag in suspend path

Suspend flow was always programming wakeup sources with a fixed
secure flag, regardless of whether the caller was secure or
non-secure. This may cause incorrect behavior for non-secure
suspend requests.

Fix this by passing the caller's security state (flag) through
pm_client_suspend() and pm_client_set_wakeup_sources() to ensure
that wakeup sources are set with the correct context.

Fixes: <4697164a3fa8> ("plat: xilinx: versal: Mark IPI calls secure/non-secure")

Change-Id: I5fcf65788a54010b4759b0d08e4f54c6e5037e47
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

show more ...

feat(zynqmp): mark IPI calls secure/non-secure

Use BIT24 of the IPI command header from payload[0] to identify the
caller's security state. If the SMC caller is non-secure, set BIT24
to indicate a n

feat(zynqmp): mark IPI calls secure/non-secure

Use BIT24 of the IPI command header from payload[0] to identify the
caller's security state. If the SMC caller is non-secure, set BIT24
to indicate a non-secure origin.

The mechanism is already present in Versal, Versal NET, and
Versal Gen 2 platforms. Extend the same support to Zynq UltraScale+
MPSoC (ZU+) to align its behavior with newer SoCs.

Change-Id: Ic77926033e76a53c0fa1a9949e6838ec64bd6ae5
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

show more ...

fix(cpus): inform the compiler that struct cpu_ops is aligned

The only way to access a cpu_ops structure is through a pointer returned
from assembly so the compiler can't know its alignment and it m

fix(cpus): inform the compiler that struct cpu_ops is aligned

The only way to access a cpu_ops structure is through a pointer returned
from assembly so the compiler can't know its alignment and it must
assume the worst. As a result, it's scared to do 64 bit loads and must
do 8 single byte loads that it then can combine together.

Well, the cpu assembly macros take care to align the cpu_ops entries to
a word boundary so we can propagate that information to the structure
definition as well and removed the compiler's paranoia.

Change-Id: Id38d6f1b92527b8a414cfbb856a5a82c76a1b1a8
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

refactor(el3-runtime): move the initialisation of the cpu_ops_ptr to C

The difference between AArch32 and AArch64 is insignificant and the
usage is identical. The only thing that required the use of

refactor(el3-runtime): move the initialisation of the cpu_ops_ptr to C

The difference between AArch32 and AArch64 is insignificant and the
usage is identical. The only thing that required the use of assembly was
that the get_cpu_ops_ptr() function was not PCS compliant and needed a
wrapper to do that instead. That has now been fixed so move this to C so
it's more readable and more optimise-able by the compiler.

Change-Id: I5fcfe8ddb122dd35d58adc6d44a7484c5c595815
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

fix(arm): increase reserved DRAM1 mem for NS images

Defconfig kernels are now approaching 50MB, making the previous 64MB
allocation for both the kernel and initrd insufficient. To accommodate
this g

fix(arm): increase reserved DRAM1 mem for NS images

Defconfig kernels are now approaching 50MB, making the previous 64MB
allocation for both the kernel and initrd insufficient. To accommodate
this growth, increase the reserved NS memory to 128MB.

Change-Id: Ifffdda4623ec7930e4c830a6a222933807d09882
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

show more ...

feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support

Implement support for FEAT_MPAM_PE_BW_CTRL, allowing lower
Exception Levels to access MPAM_PE_BW_CTRL control registers
by disabling their traps to

feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support

Implement support for FEAT_MPAM_PE_BW_CTRL, allowing lower
Exception Levels to access MPAM_PE_BW_CTRL control registers
by disabling their traps to EL3.

When INIT_UNUSED_NS_EL2=1, configure MPAMBW2_EL2 in EL3 so
that MPAM_PE_BW_CTRL accesses from EL0/EL1 do not trap to EL2.

At this stage, PE-side MPAM bandwidth controls remain disabled
in EL3.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I8e359b0eb912cff3bdda109b21727a627cac3a7e

show more ...

fix(st-clock): add ck_bus_risaf4 clock for STM32MP2

Add management of the ck_bus_risaf4 clock.
The RISAF4 clock is missing, which causes a panic if it is enabled.
The DDR clock is set to critical as

fix(st-clock): add ck_bus_risaf4 clock for STM32MP2

Add management of the ck_bus_risaf4 clock.
The RISAF4 clock is missing, which causes a panic if it is enabled.
The DDR clock is set to critical as it is mandatory to keep the DDR
clock active.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change-Id: I6ac2aff07484bfc22210ee9d3e46a97d1735f34b

show more ...

Merge changes from topic "xlnx_misra_fix_gen_common" into integration

* changes:
fix(common): initialize the variables
fix(common): rename exit label
fix(common): add missing curly braces
fi

Merge changes from topic "xlnx_misra_fix_gen_common" into integration

* changes:
fix(common): initialize the variables
fix(common): rename exit label
fix(common): add missing curly braces
fix(common): add missing curly braces

show more ...

Merge changes from topic "xlnx_armclang_fix" into integration

* changes:
fix(versal2): move plat_core_pos_by_mpidr to asm
fix(versal-net): move plat_core_pos_by_mpidr to asm

Merge "fix(drtm): remove plat_system_reset()" into integration

Merge "feat(drtm): remove todo that is implemented" into integration

feat(spmd): add FFA_NS_RES_INFO_GET ABI

Call should be forwarded to the SPMC from the NWd,
but not the other way around.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: Ic0951ffc6610c31f94fe

feat(spmd): add FFA_NS_RES_INFO_GET ABI

Call should be forwarded to the SPMC from the NWd,
but not the other way around.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: Ic0951ffc6610c31f94fec5fd38f07a8081f35d94

show more ...

feat(cpus): add support for Canyon CPU

Add basic CPU library code to support the Canyon CPU.

Change-Id: I82edc4384c4fe35ec2cf6b4bfd877a24ad8725dc
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
S

feat(cpus): add support for Canyon CPU

Add basic CPU library code to support the Canyon CPU.

Change-Id: I82edc4384c4fe35ec2cf6b4bfd877a24ad8725dc
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
Signed-off-by: Min Yao Ng <minyao.ng@arm.com>
Signed-off-by: Aditya Deshpande <aditya.deshpande@arm.com>

show more ...

Merge "fix(tools): renesas: rzg: Fix tool build" into integration

Merge "fix(simd): enforce FP regs context mgmt when SVE regs are enabled" into integration

Merge changes from topic "xlnx_misra_fix_gen_gicv3" into integration

* changes:
fix(gicv3): typecast operands to match data type
fix(gicv3): add missing curly braces
fix(gicv3): fix misra viol

Merge changes from topic "xlnx_misra_fix_gen_gicv3" into integration

* changes:
fix(gicv3): typecast operands to match data type
fix(gicv3): add missing curly braces
fix(gicv3): fix misra violation 12.1
fix(gicv3): match function definition and declaration
fix(gicv3): typecast operands to match data type

show more ...

Merge changes from topic "xlnx_misra_fix_gen_arm" into integration

* changes:
fix(arm-drivers): add missing curly braces
fix(arm): typecast operands to match data type
fix(arm-drivers): declar

Merge changes from topic "xlnx_misra_fix_gen_arm" into integration

* changes:
fix(arm-drivers): add missing curly braces
fix(arm): typecast operands to match data type
fix(arm-drivers): declare unused parameters as void

show more ...

Merge changes from topic "xlnx_misra_fix_gen_pmuv3" into integration

* changes:
fix(lib): modify function to have single return
fix(lib): use 64-bit constants in MDCR_EL2 bit macros

Merge "fix(psci): add missing curly braces" into integration