Merge "fix(lib/psa): fix Null pointer dereference error" into integration

Merge "fix(stm32mp1): fdts: stm32mp1: align DDR regulators with new driver" into integration

build(changelog): add stm32mp13 and stm32mp15 scopes

The STM32MP1 series includes STM32MP13 and STM32MP15. As some features
may be dedicated to one SoC variant, add the 2 entries in the scopes
list.

build(changelog): add stm32mp13 and stm32mp15 scopes

The STM32MP1 series includes STM32MP13 and STM32MP15. As some features
may be dedicated to one SoC variant, add the 2 entries in the scopes
list.
While at it, correct the title for STM32MP1.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I521d0e1dfdda0638ab9970c93821cf08efbd183a

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fix(stm32mp1): fdts: stm32mp1: align DDR regulators with new driver

With recent changes, TF-A now panics on MC-1, Avenger96 and Odyssey:

NOTICE: CPU: STM32MP157C?? Rev.B
NOTICE: Model: Linux

fix(stm32mp1): fdts: stm32mp1: align DDR regulators with new driver

With recent changes, TF-A now panics on MC-1, Avenger96 and Odyssey:

NOTICE: CPU: STM32MP157C?? Rev.B
NOTICE: Model: Linux Automation MC-1 board
ERROR: regul ldo3: max value 750 is invalid
PANIC at PC : 0x2ffeebb7

as the driver takes great offense at the content of the device
tree. The parts in question were copy-pasted from ST DTs, but
those ST DTs were fixed by commit 67d95409baae
("refactor(stm32mp1-fdts): update regulator description").

Fix the breakage by transplanting the same changes into all
remaining STM32MP1 DTs.

Change was boot-tested on MC-1, but only build tested for the
other two.

Fixes: bba9fdee589f ("feat(stm32mp1): add regulator framework compilation")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Change-Id: I143d0091625f62c313b3b71449c9ad99583d01c8

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Merge "docs(changelog): changelog for v2.7 release" into integration

docs(changelog): changelog for v2.7 release

Change-Id: I573e5eb3c7fad097892292c8a967dc02d72d12e6
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

Merge changes from topic "sb/threat-model" into integration

* changes:
docs(threat-model): broaden the scope of threat #05
docs(threat-model): emphasize whether mitigations are implemented

Merge changes from topic "od/spm-doc-update" into integration

* changes:
docs(spm): refresh FF-A SPM design doc
docs(spm): update FF-A manifest binding

docs(spm): refresh FF-A SPM design doc

- Move manifest binding doc as a dedicated SPM doc section.
- Highlight introduction of an EL3 FF-A SPM solution.
- Refresh TF-A build options.
- Refresh PE MM

docs(spm): refresh FF-A SPM design doc

- Move manifest binding doc as a dedicated SPM doc section.
- Highlight introduction of an EL3 FF-A SPM solution.
- Refresh TF-A build options.
- Refresh PE MMU configuration section.
- Add arch extensions for security hardening section.
- Minor corrections, typos fixes and rephrasing.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I2db06c140ef5871a812ce00a4398c663d5433bb4

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docs(spm): update FF-A manifest binding

- Add security state attribute to memory and device regions.
- Rename device region reg attribution to base-address aligned with
memory regions.
- Add pages

docs(spm): update FF-A manifest binding

- Add security state attribute to memory and device regions.
- Rename device region reg attribution to base-address aligned with
memory regions.
- Add pages-count field to device regions.
- Refresh interrupt attributes description in device regions.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I901f48d410edb8b10f65bb35398b80f18105e427

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docs(threat-model): broaden the scope of threat #05

- Cite crash reports as an example of sensitive
information. Previously, it might have sounded like this was the
focus of the threat.

- W

docs(threat-model): broaden the scope of threat #05

- Cite crash reports as an example of sensitive
information. Previously, it might have sounded like this was the
focus of the threat.

- Warn about logging high-precision timing information, as well as
conditionally logging (potentially nonsensitive) information
depending on sensitive information.

Change-Id: I33232dcb1e4b5c81efd4cd621b24ab5ac7b58685
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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docs(threat-model): emphasize whether mitigations are implemented

For each threat, we now separate:
- how to mitigate against it;
- whether TF-A currently implements these mitigations.

A new "Mit

docs(threat-model): emphasize whether mitigations are implemented

For each threat, we now separate:
- how to mitigate against it;
- whether TF-A currently implements these mitigations.

A new "Mitigations implemented?" box is added to each threat to
provide the implementation status. For threats that are partially
mitigated from platform code, the original text is improved to make
these expectations clearer. The hope is that platform integrators will
have an easier time identifying what they need to carefully implement
in order to follow the security recommendations from the threat model.

Change-Id: I8473d75946daf6c91a0e15e61758c183603e195b
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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Merge changes from topic "ja/boot_protocol" into integration

* changes:
docs(spm): update ff-a boot protocol documentation
docs(maintainers): add code owner to sptool

Merge "fix(include/aarch64): fix encodings for MPAMVPM* registers" into integration

docs(spm): update ff-a boot protocol documentation

Updated following sections to document implementation of the FF-A boot
information protocol:
- Describing secure partitions.
- Secure Partition Pac

docs(spm): update ff-a boot protocol documentation

Updated following sections to document implementation of the FF-A boot
information protocol:
- Describing secure partitions.
- Secure Partition Packages.
- Passing boot data to the SP.
Also updated description of the manifest field 'gp-register-num'.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I5c856437b60cdf05566dd636a01207c9b9f42e61

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Merge "fix(cpus/denver): use CPU_NO_EXTRA3_FUNC for all variants" into integration

fix(include/aarch64): fix encodings for MPAMVPM* registers

This patch fixes the following encodings in the System register
encoding space for the MPAM registers. The encodings now match
with the Arm

fix(include/aarch64): fix encodings for MPAMVPM* registers

This patch fixes the following encodings in the System register
encoding space for the MPAM registers. The encodings now match
with the Arm® Architecture Reference Manual Supplement for MPAM.

* MPAMVPM0_EL2
* MPAMVPM1_EL2
* MPAMVPM2_EL2
* MPAMVPM3_EL2
* MPAMVPM4_EL2
* MPAMVPM5_EL2
* MPAMVPM6_EL2
* MPAMVPM7_EL2
* MPAMVPMV_EL2

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ib339412de6a9c945a3307f3f347fe7b2efabdc18

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fix(measured-boot): add SP entries to event_log_metadata

Add SP entries to event_log_metadata if SPD_spmd is enabled. Otherwise
the platform cannot boot with measured boot enabled.

Signed-off-by: I

fix(measured-boot): add SP entries to event_log_metadata

Add SP entries to event_log_metadata if SPD_spmd is enabled. Otherwise
the platform cannot boot with measured boot enabled.

Signed-off-by: Imre Kis <imre.kis@arm.com>
Change-Id: I525eb50e7bb60796b63a8c7f81962983017bbf87

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fix(versal): resolve misra 15.6 warnings

MISRA Violation: MISRA-C:2012 R.15.6
- The body of an iteration-statement or a selection-statement shall be
a compound statement.

Signed-off-by: Venkatesh Y

fix(versal): resolve misra 15.6 warnings

MISRA Violation: MISRA-C:2012 R.15.6
- The body of an iteration-statement or a selection-statement shall be
a compound statement.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: Ia1d6fcabd36d18ff2dab6c22579ffafd5211fc1f

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feat(imx8mq): add 100us delay after USB OTG SRC bit 0 clear

After the SRC bit clear, we must wait for a while to make sure
the operation is finished. And don't enable all the PU domains
by default.

feat(imx8mq): add 100us delay after USB OTG SRC bit 0 clear

After the SRC bit clear, we must wait for a while to make sure
the operation is finished. And don't enable all the PU domains
by default.

for USB OTG, the limitations are:
1. before system clock configuration. ipg clock runs at 12.5MHz.
delay time should longer than 82us.

2. after system clock configuration. ipg clock runs at 66.5MHz.
delay time should longer than 15.3us.

so add udelay 100 to safely clear the SRC bit 0.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I52e8e7739fdaaf86442bcd148e768b6af38bcdb7

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docs(maintainers): add code owner to sptool

Add Joao Alves as code owner to the sptool.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I9e44e322ba1cce62308bf16c4a6253f7b0117fe0

fix(cpus/denver): use CPU_NO_EXTRA3_FUNC for all variants

Denver CPUs use the same workaround for CVE-2017-5715 and CVE-2022-23960
vulnerabilities. The workaround for CVE-2017-5715 is always enabled

fix(cpus/denver): use CPU_NO_EXTRA3_FUNC for all variants

Denver CPUs use the same workaround for CVE-2017-5715 and CVE-2022-23960
vulnerabilities. The workaround for CVE-2017-5715 is always enabled, so
all Denver variants use CPU_NO_EXTRA3_FUNC as a placeholder for the
mitigation for CVE-2022-23960. This patch implements the approach.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I0863541ce19b6b3b6d1b2f901d3fb6a77f315189

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Merge "fix(build): use DWARF 4 when building debug" into integration

Merge changes from topic "ffa_el3_spmc" into integration

* changes:
fix(spmc): fix incorrect FF-A version usage
fix(spmc): fix FF-A memory transaction validation

fix(zynqmp): resolve misra 8.13 warnings

MISRA Violation: MISRA-C:2012 R.8.13
- The pointer variable points to a non-constant type
but does not modify the object it points to. Consider
adding const

fix(zynqmp): resolve misra 8.13 warnings

MISRA Violation: MISRA-C:2012 R.8.13
- The pointer variable points to a non-constant type
but does not modify the object it points to. Consider
adding const qualifier to the points-to type.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: Ifd06c789cfd3babe1f5c0a17aff1ce8e70c87b05

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