1 /* 2 * Copyright (c) 2018-2022, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <arch.h> 12 #include <arch_helpers.h> 13 #include <common/debug.h> 14 #include <drivers/clk.h> 15 #include <drivers/delay_timer.h> 16 #include <drivers/mmc.h> 17 #include <drivers/st/stm32_gpio.h> 18 #include <drivers/st/stm32_sdmmc2.h> 19 #include <drivers/st/stm32mp_reset.h> 20 #include <lib/mmio.h> 21 #include <lib/utils.h> 22 #include <libfdt.h> 23 #include <plat/common/platform.h> 24 25 #include <platform_def.h> 26 27 /* Registers offsets */ 28 #define SDMMC_POWER 0x00U 29 #define SDMMC_CLKCR 0x04U 30 #define SDMMC_ARGR 0x08U 31 #define SDMMC_CMDR 0x0CU 32 #define SDMMC_RESPCMDR 0x10U 33 #define SDMMC_RESP1R 0x14U 34 #define SDMMC_RESP2R 0x18U 35 #define SDMMC_RESP3R 0x1CU 36 #define SDMMC_RESP4R 0x20U 37 #define SDMMC_DTIMER 0x24U 38 #define SDMMC_DLENR 0x28U 39 #define SDMMC_DCTRLR 0x2CU 40 #define SDMMC_DCNTR 0x30U 41 #define SDMMC_STAR 0x34U 42 #define SDMMC_ICR 0x38U 43 #define SDMMC_MASKR 0x3CU 44 #define SDMMC_ACKTIMER 0x40U 45 #define SDMMC_IDMACTRLR 0x50U 46 #define SDMMC_IDMABSIZER 0x54U 47 #define SDMMC_IDMABASE0R 0x58U 48 #define SDMMC_IDMABASE1R 0x5CU 49 #define SDMMC_FIFOR 0x80U 50 51 /* SDMMC power control register */ 52 #define SDMMC_POWER_PWRCTRL GENMASK(1, 0) 53 #define SDMMC_POWER_PWRCTRL_PWR_CYCLE BIT(1) 54 #define SDMMC_POWER_DIRPOL BIT(4) 55 56 /* SDMMC clock control register */ 57 #define SDMMC_CLKCR_WIDBUS_4 BIT(14) 58 #define SDMMC_CLKCR_WIDBUS_8 BIT(15) 59 #define SDMMC_CLKCR_NEGEDGE BIT(16) 60 #define SDMMC_CLKCR_HWFC_EN BIT(17) 61 #define SDMMC_CLKCR_SELCLKRX_0 BIT(20) 62 63 /* SDMMC command register */ 64 #define SDMMC_CMDR_CMDTRANS BIT(6) 65 #define SDMMC_CMDR_CMDSTOP BIT(7) 66 #define SDMMC_CMDR_WAITRESP GENMASK(9, 8) 67 #define SDMMC_CMDR_WAITRESP_SHORT BIT(8) 68 #define SDMMC_CMDR_WAITRESP_SHORT_NOCRC BIT(9) 69 #define SDMMC_CMDR_CPSMEN BIT(12) 70 71 /* SDMMC data control register */ 72 #define SDMMC_DCTRLR_DTEN BIT(0) 73 #define SDMMC_DCTRLR_DTDIR BIT(1) 74 #define SDMMC_DCTRLR_DTMODE GENMASK(3, 2) 75 #define SDMMC_DCTRLR_DBLOCKSIZE GENMASK(7, 4) 76 #define SDMMC_DCTRLR_DBLOCKSIZE_SHIFT 4 77 #define SDMMC_DCTRLR_FIFORST BIT(13) 78 79 #define SDMMC_DCTRLR_CLEAR_MASK (SDMMC_DCTRLR_DTEN | \ 80 SDMMC_DCTRLR_DTDIR | \ 81 SDMMC_DCTRLR_DTMODE | \ 82 SDMMC_DCTRLR_DBLOCKSIZE) 83 84 /* SDMMC status register */ 85 #define SDMMC_STAR_CCRCFAIL BIT(0) 86 #define SDMMC_STAR_DCRCFAIL BIT(1) 87 #define SDMMC_STAR_CTIMEOUT BIT(2) 88 #define SDMMC_STAR_DTIMEOUT BIT(3) 89 #define SDMMC_STAR_TXUNDERR BIT(4) 90 #define SDMMC_STAR_RXOVERR BIT(5) 91 #define SDMMC_STAR_CMDREND BIT(6) 92 #define SDMMC_STAR_CMDSENT BIT(7) 93 #define SDMMC_STAR_DATAEND BIT(8) 94 #define SDMMC_STAR_DBCKEND BIT(10) 95 #define SDMMC_STAR_DPSMACT BIT(12) 96 #define SDMMC_STAR_RXFIFOHF BIT(15) 97 #define SDMMC_STAR_RXFIFOE BIT(19) 98 #define SDMMC_STAR_IDMATE BIT(27) 99 #define SDMMC_STAR_IDMABTC BIT(28) 100 101 /* SDMMC DMA control register */ 102 #define SDMMC_IDMACTRLR_IDMAEN BIT(0) 103 104 #define SDMMC_STATIC_FLAGS (SDMMC_STAR_CCRCFAIL | \ 105 SDMMC_STAR_DCRCFAIL | \ 106 SDMMC_STAR_CTIMEOUT | \ 107 SDMMC_STAR_DTIMEOUT | \ 108 SDMMC_STAR_TXUNDERR | \ 109 SDMMC_STAR_RXOVERR | \ 110 SDMMC_STAR_CMDREND | \ 111 SDMMC_STAR_CMDSENT | \ 112 SDMMC_STAR_DATAEND | \ 113 SDMMC_STAR_DBCKEND | \ 114 SDMMC_STAR_IDMATE | \ 115 SDMMC_STAR_IDMABTC) 116 117 #define TIMEOUT_US_1_MS 1000U 118 #define TIMEOUT_US_10_MS 10000U 119 #define TIMEOUT_US_1_S 1000000U 120 121 /* Power cycle delays in ms */ 122 #define VCC_POWER_OFF_DELAY 2 123 #define VCC_POWER_ON_DELAY 2 124 #define POWER_CYCLE_DELAY 2 125 #define POWER_OFF_DELAY 2 126 #define POWER_ON_DELAY 1 127 128 #ifndef DT_SDMMC2_COMPAT 129 #define DT_SDMMC2_COMPAT "st,stm32-sdmmc2" 130 #endif 131 132 static void stm32_sdmmc2_init(void); 133 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd); 134 static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd); 135 static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width); 136 static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size); 137 static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size); 138 static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size); 139 140 static const struct mmc_ops stm32_sdmmc2_ops = { 141 .init = stm32_sdmmc2_init, 142 .send_cmd = stm32_sdmmc2_send_cmd, 143 .set_ios = stm32_sdmmc2_set_ios, 144 .prepare = stm32_sdmmc2_prepare, 145 .read = stm32_sdmmc2_read, 146 .write = stm32_sdmmc2_write, 147 }; 148 149 static struct stm32_sdmmc2_params sdmmc2_params; 150 151 static bool next_cmd_is_acmd; 152 153 #pragma weak plat_sdmmc2_use_dma 154 bool plat_sdmmc2_use_dma(unsigned int instance, unsigned int memory) 155 { 156 return false; 157 } 158 159 static void stm32_sdmmc2_init(void) 160 { 161 uint32_t clock_div; 162 uint32_t freq = STM32MP_MMC_INIT_FREQ; 163 uintptr_t base = sdmmc2_params.reg_base; 164 int ret; 165 166 if (sdmmc2_params.max_freq != 0U) { 167 freq = MIN(sdmmc2_params.max_freq, freq); 168 } 169 170 if (sdmmc2_params.vmmc_regu != NULL) { 171 ret = regulator_disable(sdmmc2_params.vmmc_regu); 172 if (ret < 0) { 173 panic(); 174 } 175 } 176 177 mdelay(VCC_POWER_OFF_DELAY); 178 179 mmio_write_32(base + SDMMC_POWER, 180 SDMMC_POWER_PWRCTRL_PWR_CYCLE | sdmmc2_params.dirpol); 181 mdelay(POWER_CYCLE_DELAY); 182 183 if (sdmmc2_params.vmmc_regu != NULL) { 184 ret = regulator_enable(sdmmc2_params.vmmc_regu); 185 if (ret < 0) { 186 panic(); 187 } 188 } 189 190 mdelay(VCC_POWER_ON_DELAY); 191 192 mmio_write_32(base + SDMMC_POWER, sdmmc2_params.dirpol); 193 mdelay(POWER_OFF_DELAY); 194 195 clock_div = div_round_up(sdmmc2_params.clk_rate, freq * 2U); 196 197 mmio_write_32(base + SDMMC_CLKCR, SDMMC_CLKCR_HWFC_EN | clock_div | 198 sdmmc2_params.negedge | 199 sdmmc2_params.pin_ckin); 200 201 mmio_write_32(base + SDMMC_POWER, 202 SDMMC_POWER_PWRCTRL | sdmmc2_params.dirpol); 203 204 mdelay(POWER_ON_DELAY); 205 } 206 207 static int stm32_sdmmc2_stop_transfer(void) 208 { 209 struct mmc_cmd cmd_stop; 210 211 zeromem(&cmd_stop, sizeof(struct mmc_cmd)); 212 213 cmd_stop.cmd_idx = MMC_CMD(12); 214 cmd_stop.resp_type = MMC_RESPONSE_R1B; 215 216 return stm32_sdmmc2_send_cmd(&cmd_stop); 217 } 218 219 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd) 220 { 221 uint64_t timeout; 222 uint32_t flags_cmd, status; 223 uint32_t flags_data = 0; 224 int err = 0; 225 uintptr_t base = sdmmc2_params.reg_base; 226 unsigned int cmd_reg, arg_reg; 227 228 if (cmd == NULL) { 229 return -EINVAL; 230 } 231 232 flags_cmd = SDMMC_STAR_CTIMEOUT; 233 arg_reg = cmd->cmd_arg; 234 235 if ((mmio_read_32(base + SDMMC_CMDR) & SDMMC_CMDR_CPSMEN) != 0U) { 236 mmio_write_32(base + SDMMC_CMDR, 0); 237 } 238 239 cmd_reg = cmd->cmd_idx | SDMMC_CMDR_CPSMEN; 240 241 if (cmd->resp_type == 0U) { 242 flags_cmd |= SDMMC_STAR_CMDSENT; 243 } 244 245 if ((cmd->resp_type & MMC_RSP_48) != 0U) { 246 if ((cmd->resp_type & MMC_RSP_136) != 0U) { 247 flags_cmd |= SDMMC_STAR_CMDREND; 248 cmd_reg |= SDMMC_CMDR_WAITRESP; 249 } else if ((cmd->resp_type & MMC_RSP_CRC) != 0U) { 250 flags_cmd |= SDMMC_STAR_CMDREND | SDMMC_STAR_CCRCFAIL; 251 cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT; 252 } else { 253 flags_cmd |= SDMMC_STAR_CMDREND; 254 cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT_NOCRC; 255 } 256 } 257 258 switch (cmd->cmd_idx) { 259 case MMC_CMD(1): 260 arg_reg |= OCR_POWERUP; 261 break; 262 case MMC_CMD(6): 263 if ((sdmmc2_params.device_info->mmc_dev_type == MMC_IS_SD_HC) && 264 (!next_cmd_is_acmd)) { 265 cmd_reg |= SDMMC_CMDR_CMDTRANS; 266 if (sdmmc2_params.use_dma) { 267 flags_data |= SDMMC_STAR_DCRCFAIL | 268 SDMMC_STAR_DTIMEOUT | 269 SDMMC_STAR_DATAEND | 270 SDMMC_STAR_RXOVERR | 271 SDMMC_STAR_IDMATE | 272 SDMMC_STAR_DBCKEND; 273 } 274 } 275 break; 276 case MMC_CMD(8): 277 if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) { 278 cmd_reg |= SDMMC_CMDR_CMDTRANS; 279 } 280 break; 281 case MMC_CMD(12): 282 cmd_reg |= SDMMC_CMDR_CMDSTOP; 283 break; 284 case MMC_CMD(17): 285 case MMC_CMD(18): 286 cmd_reg |= SDMMC_CMDR_CMDTRANS; 287 if (sdmmc2_params.use_dma) { 288 flags_data |= SDMMC_STAR_DCRCFAIL | 289 SDMMC_STAR_DTIMEOUT | 290 SDMMC_STAR_DATAEND | 291 SDMMC_STAR_RXOVERR | 292 SDMMC_STAR_IDMATE; 293 } 294 break; 295 case MMC_ACMD(41): 296 arg_reg |= OCR_3_2_3_3 | OCR_3_3_3_4; 297 break; 298 case MMC_ACMD(51): 299 cmd_reg |= SDMMC_CMDR_CMDTRANS; 300 if (sdmmc2_params.use_dma) { 301 flags_data |= SDMMC_STAR_DCRCFAIL | 302 SDMMC_STAR_DTIMEOUT | 303 SDMMC_STAR_DATAEND | 304 SDMMC_STAR_RXOVERR | 305 SDMMC_STAR_IDMATE | 306 SDMMC_STAR_DBCKEND; 307 } 308 break; 309 default: 310 break; 311 } 312 313 next_cmd_is_acmd = (cmd->cmd_idx == MMC_CMD(55)); 314 315 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 316 317 /* 318 * Clear the SDMMC_DCTRLR if the command does not await data. 319 * Skip CMD55 as the next command could be data related, and 320 * the register could have been set in prepare function. 321 */ 322 if (((cmd_reg & SDMMC_CMDR_CMDTRANS) == 0U) && !next_cmd_is_acmd) { 323 mmio_write_32(base + SDMMC_DCTRLR, 0U); 324 } 325 326 if ((cmd->resp_type & MMC_RSP_BUSY) != 0U) { 327 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX); 328 } 329 330 mmio_write_32(base + SDMMC_ARGR, arg_reg); 331 332 mmio_write_32(base + SDMMC_CMDR, cmd_reg); 333 334 status = mmio_read_32(base + SDMMC_STAR); 335 336 timeout = timeout_init_us(TIMEOUT_US_10_MS); 337 338 while ((status & flags_cmd) == 0U) { 339 if (timeout_elapsed(timeout)) { 340 err = -ETIMEDOUT; 341 ERROR("%s: timeout 10ms (cmd = %u,status = %x)\n", 342 __func__, cmd->cmd_idx, status); 343 goto err_exit; 344 } 345 346 status = mmio_read_32(base + SDMMC_STAR); 347 } 348 349 if ((status & (SDMMC_STAR_CTIMEOUT | SDMMC_STAR_CCRCFAIL)) != 0U) { 350 if ((status & SDMMC_STAR_CTIMEOUT) != 0U) { 351 err = -ETIMEDOUT; 352 /* 353 * Those timeouts can occur, and framework will handle 354 * the retries. CMD8 is expected to return this timeout 355 * for eMMC 356 */ 357 if (!((cmd->cmd_idx == MMC_CMD(1)) || 358 (cmd->cmd_idx == MMC_CMD(13)) || 359 ((cmd->cmd_idx == MMC_CMD(8)) && 360 (cmd->resp_type == MMC_RESPONSE_R7)))) { 361 ERROR("%s: CTIMEOUT (cmd = %u,status = %x)\n", 362 __func__, cmd->cmd_idx, status); 363 } 364 } else { 365 err = -EIO; 366 ERROR("%s: CRCFAIL (cmd = %u,status = %x)\n", 367 __func__, cmd->cmd_idx, status); 368 } 369 370 goto err_exit; 371 } 372 373 if ((cmd_reg & SDMMC_CMDR_WAITRESP) != 0U) { 374 if ((cmd->cmd_idx == MMC_CMD(9)) && 375 ((cmd_reg & SDMMC_CMDR_WAITRESP) == SDMMC_CMDR_WAITRESP)) { 376 /* Need to invert response to match CSD structure */ 377 cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP4R); 378 cmd->resp_data[1] = mmio_read_32(base + SDMMC_RESP3R); 379 cmd->resp_data[2] = mmio_read_32(base + SDMMC_RESP2R); 380 cmd->resp_data[3] = mmio_read_32(base + SDMMC_RESP1R); 381 } else { 382 cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP1R); 383 if ((cmd_reg & SDMMC_CMDR_WAITRESP) == 384 SDMMC_CMDR_WAITRESP) { 385 cmd->resp_data[1] = mmio_read_32(base + 386 SDMMC_RESP2R); 387 cmd->resp_data[2] = mmio_read_32(base + 388 SDMMC_RESP3R); 389 cmd->resp_data[3] = mmio_read_32(base + 390 SDMMC_RESP4R); 391 } 392 } 393 } 394 395 if (flags_data == 0U) { 396 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 397 398 return 0; 399 } 400 401 status = mmio_read_32(base + SDMMC_STAR); 402 403 timeout = timeout_init_us(TIMEOUT_US_10_MS); 404 405 while ((status & flags_data) == 0U) { 406 if (timeout_elapsed(timeout)) { 407 ERROR("%s: timeout 10ms (cmd = %u,status = %x)\n", 408 __func__, cmd->cmd_idx, status); 409 err = -ETIMEDOUT; 410 goto err_exit; 411 } 412 413 status = mmio_read_32(base + SDMMC_STAR); 414 }; 415 416 if ((status & (SDMMC_STAR_DTIMEOUT | SDMMC_STAR_DCRCFAIL | 417 SDMMC_STAR_TXUNDERR | SDMMC_STAR_RXOVERR | 418 SDMMC_STAR_IDMATE)) != 0U) { 419 ERROR("%s: Error flag (cmd = %u,status = %x)\n", __func__, 420 cmd->cmd_idx, status); 421 err = -EIO; 422 } 423 424 err_exit: 425 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 426 mmio_clrbits_32(base + SDMMC_CMDR, SDMMC_CMDR_CMDTRANS); 427 428 if ((err != 0) && ((status & SDMMC_STAR_DPSMACT) != 0U)) { 429 int ret_stop = stm32_sdmmc2_stop_transfer(); 430 431 if (ret_stop != 0) { 432 return ret_stop; 433 } 434 } 435 436 return err; 437 } 438 439 static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd) 440 { 441 uint8_t retry; 442 int err; 443 444 assert(cmd != NULL); 445 446 for (retry = 0U; retry < 3U; retry++) { 447 err = stm32_sdmmc2_send_cmd_req(cmd); 448 if (err == 0) { 449 return 0; 450 } 451 452 if ((cmd->cmd_idx == MMC_CMD(1)) || 453 (cmd->cmd_idx == MMC_CMD(13))) { 454 return 0; /* Retry managed by framework */ 455 } 456 457 /* Command 8 is expected to fail for eMMC */ 458 if (cmd->cmd_idx != MMC_CMD(8)) { 459 WARN(" CMD%u, Retry: %u, Error: %d\n", 460 cmd->cmd_idx, retry + 1U, err); 461 } 462 463 udelay(10U); 464 } 465 466 return err; 467 } 468 469 static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width) 470 { 471 uintptr_t base = sdmmc2_params.reg_base; 472 uint32_t bus_cfg = 0; 473 uint32_t clock_div, max_freq, freq; 474 uint32_t clk_rate = sdmmc2_params.clk_rate; 475 uint32_t max_bus_freq = sdmmc2_params.device_info->max_bus_freq; 476 477 switch (width) { 478 case MMC_BUS_WIDTH_1: 479 break; 480 case MMC_BUS_WIDTH_4: 481 bus_cfg |= SDMMC_CLKCR_WIDBUS_4; 482 break; 483 case MMC_BUS_WIDTH_8: 484 bus_cfg |= SDMMC_CLKCR_WIDBUS_8; 485 break; 486 default: 487 panic(); 488 break; 489 } 490 491 if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) { 492 if (max_bus_freq >= 52000000U) { 493 max_freq = STM32MP_EMMC_HIGH_SPEED_MAX_FREQ; 494 } else { 495 max_freq = STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ; 496 } 497 } else { 498 if (max_bus_freq >= 50000000U) { 499 max_freq = STM32MP_SD_HIGH_SPEED_MAX_FREQ; 500 } else { 501 max_freq = STM32MP_SD_NORMAL_SPEED_MAX_FREQ; 502 } 503 } 504 505 if (sdmmc2_params.max_freq != 0U) { 506 freq = MIN(sdmmc2_params.max_freq, max_freq); 507 } else { 508 freq = max_freq; 509 } 510 511 clock_div = div_round_up(clk_rate, freq * 2U); 512 513 mmio_write_32(base + SDMMC_CLKCR, 514 SDMMC_CLKCR_HWFC_EN | clock_div | bus_cfg | 515 sdmmc2_params.negedge | 516 sdmmc2_params.pin_ckin); 517 518 return 0; 519 } 520 521 static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size) 522 { 523 struct mmc_cmd cmd; 524 int ret; 525 uintptr_t base = sdmmc2_params.reg_base; 526 uint32_t data_ctrl = SDMMC_DCTRLR_DTDIR; 527 uint32_t arg_size; 528 529 assert(size != 0U); 530 531 if (size > MMC_BLOCK_SIZE) { 532 arg_size = MMC_BLOCK_SIZE; 533 } else { 534 arg_size = size; 535 } 536 537 sdmmc2_params.use_dma = plat_sdmmc2_use_dma(base, buf); 538 539 if (sdmmc2_params.use_dma) { 540 inv_dcache_range(buf, size); 541 } 542 543 /* Prepare CMD 16*/ 544 mmio_write_32(base + SDMMC_DTIMER, 0); 545 546 mmio_write_32(base + SDMMC_DLENR, 0); 547 548 mmio_write_32(base + SDMMC_DCTRLR, 0); 549 550 zeromem(&cmd, sizeof(struct mmc_cmd)); 551 552 cmd.cmd_idx = MMC_CMD(16); 553 cmd.cmd_arg = arg_size; 554 cmd.resp_type = MMC_RESPONSE_R1; 555 556 ret = stm32_sdmmc2_send_cmd(&cmd); 557 if (ret != 0) { 558 ERROR("CMD16 failed\n"); 559 return ret; 560 } 561 562 /* Prepare data command */ 563 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX); 564 565 mmio_write_32(base + SDMMC_DLENR, size); 566 567 if (sdmmc2_params.use_dma) { 568 mmio_write_32(base + SDMMC_IDMACTRLR, 569 SDMMC_IDMACTRLR_IDMAEN); 570 mmio_write_32(base + SDMMC_IDMABASE0R, buf); 571 572 flush_dcache_range(buf, size); 573 } 574 575 data_ctrl |= __builtin_ctz(arg_size) << SDMMC_DCTRLR_DBLOCKSIZE_SHIFT; 576 577 mmio_clrsetbits_32(base + SDMMC_DCTRLR, 578 SDMMC_DCTRLR_CLEAR_MASK, 579 data_ctrl); 580 581 return 0; 582 } 583 584 static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size) 585 { 586 uint32_t error_flags = SDMMC_STAR_RXOVERR | SDMMC_STAR_DCRCFAIL | 587 SDMMC_STAR_DTIMEOUT; 588 uint32_t flags = error_flags | SDMMC_STAR_DATAEND; 589 uint32_t status; 590 uint32_t *buffer; 591 uintptr_t base = sdmmc2_params.reg_base; 592 uintptr_t fifo_reg = base + SDMMC_FIFOR; 593 uint64_t timeout; 594 int ret; 595 596 /* Assert buf is 4 bytes aligned */ 597 assert((buf & GENMASK(1, 0)) == 0U); 598 599 buffer = (uint32_t *)buf; 600 601 if (sdmmc2_params.use_dma) { 602 inv_dcache_range(buf, size); 603 604 return 0; 605 } 606 607 if (size <= MMC_BLOCK_SIZE) { 608 flags |= SDMMC_STAR_DBCKEND; 609 } 610 611 timeout = timeout_init_us(TIMEOUT_US_1_S); 612 613 do { 614 status = mmio_read_32(base + SDMMC_STAR); 615 616 if ((status & error_flags) != 0U) { 617 ERROR("%s: Read error (status = %x)\n", __func__, 618 status); 619 mmio_write_32(base + SDMMC_DCTRLR, 620 SDMMC_DCTRLR_FIFORST); 621 622 mmio_write_32(base + SDMMC_ICR, 623 SDMMC_STATIC_FLAGS); 624 625 ret = stm32_sdmmc2_stop_transfer(); 626 if (ret != 0) { 627 return ret; 628 } 629 630 return -EIO; 631 } 632 633 if (timeout_elapsed(timeout)) { 634 ERROR("%s: timeout 1s (status = %x)\n", 635 __func__, status); 636 mmio_write_32(base + SDMMC_ICR, 637 SDMMC_STATIC_FLAGS); 638 639 ret = stm32_sdmmc2_stop_transfer(); 640 if (ret != 0) { 641 return ret; 642 } 643 644 return -ETIMEDOUT; 645 } 646 647 if (size < (8U * sizeof(uint32_t))) { 648 if ((mmio_read_32(base + SDMMC_DCNTR) > 0U) && 649 ((status & SDMMC_STAR_RXFIFOE) == 0U)) { 650 *buffer = mmio_read_32(fifo_reg); 651 buffer++; 652 } 653 } else if ((status & SDMMC_STAR_RXFIFOHF) != 0U) { 654 uint32_t count; 655 656 /* Read data from SDMMC Rx FIFO */ 657 for (count = 0; count < 8U; count++) { 658 *buffer = mmio_read_32(fifo_reg); 659 buffer++; 660 } 661 } 662 } while ((status & flags) == 0U); 663 664 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 665 666 if ((status & SDMMC_STAR_DPSMACT) != 0U) { 667 WARN("%s: DPSMACT=1, send stop\n", __func__); 668 return stm32_sdmmc2_stop_transfer(); 669 } 670 671 return 0; 672 } 673 674 static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size) 675 { 676 return 0; 677 } 678 679 static int stm32_sdmmc2_dt_get_config(void) 680 { 681 int sdmmc_node; 682 void *fdt = NULL; 683 const fdt32_t *cuint; 684 struct dt_node_info dt_info; 685 686 if (fdt_get_address(&fdt) == 0) { 687 return -FDT_ERR_NOTFOUND; 688 } 689 690 if (fdt == NULL) { 691 return -FDT_ERR_NOTFOUND; 692 } 693 694 sdmmc_node = dt_match_instance_by_compatible(DT_SDMMC2_COMPAT, 695 sdmmc2_params.reg_base); 696 if (sdmmc_node == -FDT_ERR_NOTFOUND) { 697 return -FDT_ERR_NOTFOUND; 698 } 699 700 dt_fill_device_info(&dt_info, sdmmc_node); 701 if (dt_info.status == DT_DISABLED) { 702 return -FDT_ERR_NOTFOUND; 703 } 704 705 if (dt_set_pinctrl_config(sdmmc_node) != 0) { 706 return -FDT_ERR_BADVALUE; 707 } 708 709 sdmmc2_params.clock_id = dt_info.clock; 710 sdmmc2_params.reset_id = dt_info.reset; 711 712 if ((fdt_getprop(fdt, sdmmc_node, "st,use-ckin", NULL)) != NULL) { 713 sdmmc2_params.pin_ckin = SDMMC_CLKCR_SELCLKRX_0; 714 } 715 716 if ((fdt_getprop(fdt, sdmmc_node, "st,sig-dir", NULL)) != NULL) { 717 sdmmc2_params.dirpol = SDMMC_POWER_DIRPOL; 718 } 719 720 if ((fdt_getprop(fdt, sdmmc_node, "st,neg-edge", NULL)) != NULL) { 721 sdmmc2_params.negedge = SDMMC_CLKCR_NEGEDGE; 722 } 723 724 cuint = fdt_getprop(fdt, sdmmc_node, "bus-width", NULL); 725 if (cuint != NULL) { 726 switch (fdt32_to_cpu(*cuint)) { 727 case 4: 728 sdmmc2_params.bus_width = MMC_BUS_WIDTH_4; 729 break; 730 731 case 8: 732 sdmmc2_params.bus_width = MMC_BUS_WIDTH_8; 733 break; 734 735 default: 736 break; 737 } 738 } 739 740 cuint = fdt_getprop(fdt, sdmmc_node, "max-frequency", NULL); 741 if (cuint != NULL) { 742 sdmmc2_params.max_freq = fdt32_to_cpu(*cuint); 743 } 744 745 sdmmc2_params.vmmc_regu = regulator_get_by_supply_name(fdt, sdmmc_node, "vmmc"); 746 747 return 0; 748 } 749 750 unsigned long long stm32_sdmmc2_mmc_get_device_size(void) 751 { 752 return sdmmc2_params.device_info->device_size; 753 } 754 755 int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params) 756 { 757 assert((params != NULL) && 758 ((params->reg_base & MMC_BLOCK_MASK) == 0U) && 759 ((params->bus_width == MMC_BUS_WIDTH_1) || 760 (params->bus_width == MMC_BUS_WIDTH_4) || 761 (params->bus_width == MMC_BUS_WIDTH_8))); 762 763 memcpy(&sdmmc2_params, params, sizeof(struct stm32_sdmmc2_params)); 764 765 sdmmc2_params.vmmc_regu = NULL; 766 767 if (stm32_sdmmc2_dt_get_config() != 0) { 768 ERROR("%s: DT error\n", __func__); 769 return -ENOMEM; 770 } 771 772 clk_enable(sdmmc2_params.clock_id); 773 774 if ((int)sdmmc2_params.reset_id >= 0) { 775 int rc; 776 777 rc = stm32mp_reset_assert(sdmmc2_params.reset_id, TIMEOUT_US_1_MS); 778 if (rc != 0) { 779 panic(); 780 } 781 udelay(2); 782 rc = stm32mp_reset_deassert(sdmmc2_params.reset_id, TIMEOUT_US_1_MS); 783 if (rc != 0) { 784 panic(); 785 } 786 mdelay(1); 787 } 788 789 sdmmc2_params.clk_rate = clk_get_rate(sdmmc2_params.clock_id); 790 sdmmc2_params.device_info->ocr_voltage = OCR_3_2_3_3 | OCR_3_3_3_4; 791 792 return mmc_init(&stm32_sdmmc2_ops, sdmmc2_params.clk_rate, 793 sdmmc2_params.bus_width, sdmmc2_params.flags, 794 sdmmc2_params.device_info); 795 } 796