fix(versal2): fix misra rule 8.4 violation

Fix below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.8.4:
- A compatible declaration shall be visible when an object or
function with externa

fix(versal2): fix misra rule 8.4 violation

Fix below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.8.4:
- A compatible declaration shall be visible when an object or
function with external linkage is defined.
- Fix:
- Declare pm_secure_lock as static to give it internal linkage.

Change-Id: Ie538b2382e214ee2a486259b4ecddc12082334fa
Signed-off-by: Devanshi Chauhan <Devanshi.ChauhanAlpeshbhai@amd.com>

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fix(versal2): fix misra rule 5.7 violations

Fix below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.5.7:
- A tag name shall be a unique identifier.
- Fix:
- Rename local variables to avoid

fix(versal2): fix misra rule 5.7 violations

Fix below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.5.7:
- A tag name shall be a unique identifier.
- Fix:
- Rename local variables to avoid conflict with type names.

Change-Id: Iac8df3166dcc69ceccaaddae2134f9c8a043b3b6
Signed-off-by: Devanshi Chauhan <Devanshi.ChauhanAlpeshbhai@amd.com>

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fix(versal2): fix misra rule 18.1 violations

Fix below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.18.1:
- A pointer resulting from arithmetic on a pointer operand shall
address an elem

fix(versal2): fix misra rule 18.1 violations

Fix below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.18.1:
- A pointer resulting from arithmetic on a pointer operand shall
address an element of the same array as that pointer operand.
- Fix:
- Add upper bounds check before array access to prevent buffer
overrun.

Change-Id: I56e8201f2bf0de1d276d2ee009dafc73f08caf75
Signed-off-by: Devanshi Chauhan <Devanshi.ChauhanAlpeshbhai@amd.com>

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fix(versal2): fix misra rule 10.4 violations

Fix below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.10.4:
- Both operands of an operator in which the usual arithmetic
conversions are per

fix(versal2): fix misra rule 10.4 violations

Fix below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.10.4:
- Both operands of an operator in which the usual arithmetic
conversions are performed shall have the same essential type
category.
- Fix:
- Make operands of the same essential type category.

Change-Id: Idf3489dee8f45a5a27bda4e4392b84510352623e
Signed-off-by: Devanshi Chauhan <Devanshi.ChauhanAlpeshbhai@amd.com>

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fix(versal2): fix misra rule 10.3 violations

Fix below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.10.3:
- The value of an expression shall not be assigned to an object
with a narrower

fix(versal2): fix misra rule 10.3 violations

Fix below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.10.3:
- The value of an expression shall not be assigned to an object
with a narrower essential type or of a different essential type
category.
- Fix:
- Add explicit type casts to prevent implicit narrowing
conversions.

Change-Id: I756137cf9a403f1f6395c1d7c2d9bb70a3f6ff80
Signed-off-by: Devanshi Chauhan <Devanshi.ChauhanAlpeshbhai@amd.com>

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docs(maintainers): add George Cherian as Marvell platforms maintainer

Add George Cherian as code owner for Marvell platforms.
While at it sort the platform entry and Jaiprakash Singh's github link
a

docs(maintainers): add George Cherian as Marvell platforms maintainer

Add George Cherian as code owner for Marvell platforms.
While at it sort the platform entry and Jaiprakash Singh's github link
alphabetically.

Change-Id: I3601416faa46d99f056571c5990a426272973290
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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fix(libfdt): resolve misra 10.3 violations

The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
Replace the hard‑co

fix(libfdt): resolve misra 10.3 violations

The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
Replace the hard‑coded low‑bits mask with the LO() macro to avoid
implicit type conversions and ensure compliance with MISRA 10.3.

Change-Id: I09696e90733b101c346f4e3e3c2baf63dc1b6607
Signed-off-by: Suraj Kakade <suraj.hanumantkakade@amd.com>

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feat(lib): use C/assembler for HI/LO macros

Add conditional HI() and LO() macros so assembler/linker builds keep the
original shift‑and‑mask form, while C builds use a typed uint32_t
version for LO(

feat(lib): use C/assembler for HI/LO macros

Add conditional HI() and LO() macros so assembler/linker builds keep the
original shift‑and‑mask form, while C builds use a typed uint32_t
version for LO() to ensure correct typing and MISRA‑compliant masking.

Change-Id: I0c707c387bf8ec5742ea5600017343882682e100
Signed-off-by: Suraj Kakade <suraj.hanumantkakade@amd.com>

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Merge "fix(cpufeat): give `stxr` distinct src and ret registers" into integration

Merge "refactor(s32g274ardb): add MC RGM DDR periph macro" into integration

Merge changes I907156cb,I377ef950 into integration

* changes:
fix(mt8196): check apusys write ce binary address
fix(mt8196): increase apusys hardware semaphore timeout duration

fix(cpufeat): give `stxr` distinct src and ret registers

The stxr can cause UNDEF exceptions if the source and return
operands overlap. Add an early-clobber constraint to tell the compiler
not to do

fix(cpufeat): give `stxr` distinct src and ret registers

The stxr can cause UNDEF exceptions if the source and return
operands overlap. Add an early-clobber constraint to tell the compiler
not to do that.

Change-Id: I1d2752839e17b847f8981169eaf2798ee8fd100a
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(s32g274ardb): add training for 1D and 2D

Extend the logic for executing the training stage
to include 1D and 2D PHY training.

Change-Id: If3445125d868e67cfcd81eaeeb20b2283731a4ea
Signed-off-by

feat(s32g274ardb): add training for 1D and 2D

Extend the logic for executing the training stage
to include 1D and 2D PHY training.

Change-Id: If3445125d868e67cfcd81eaeeb20b2283731a4ea
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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feat(s32g274ardb): add DDR training stubs

Introduce logic to load DDR firmware configuration
data from memory into internal structures.

Introduce the components required to initialize
the DDR contr

feat(s32g274ardb): add DDR training stubs

Introduce logic to load DDR firmware configuration
data from memory into internal structures.

Introduce the components required to initialize
the DDR controller and prepare for PHY training.
It includes controller setup and the training
orchestration function.

Change-Id: Icd8649516d9bad1a6d72616a774b8b60c6bae067
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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refactor(s32g274ardb): add MC RGM DDR periph macro

Replace value with MC_RGM_DDR_PERIPH macro
to clearly identify the DDR peripheral ID
used in MC_RGM register operations.

Change-Id: I43756e5df068f

refactor(s32g274ardb): add MC RGM DDR periph macro

Replace value with MC_RGM_DDR_PERIPH macro
to clearly identify the DDR peripheral ID
used in MC_RGM register operations.

Change-Id: I43756e5df068fb4f523b37a9db3a4a9ce8be836a
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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fix(mt8196): check apusys write ce binary address

The address and value to be written to the CE bin are set by the image
loaded by the kernel.
Check the address to ensure that no illegal address is

fix(mt8196): check apusys write ce binary address

The address and value to be written to the CE bin are set by the image
loaded by the kernel.
Check the address to ensure that no illegal address is accessed.

Change-Id: I907156cb9f304825839433cae0e31b319abc22bd
Signed-off-by: Yuan-chang Hsieh <yuan-chang.hsieh@mediatek.corp-partner.google.com>

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fix(mt8196): increase apusys hardware semaphore timeout duration

Increase the hw semaphore timeout duration because the kernel may
occasionally fail to acquire semaphore, resulting in power on/off
f

fix(mt8196): increase apusys hardware semaphore timeout duration

Increase the hw semaphore timeout duration because the kernel may
occasionally fail to acquire semaphore, resulting in power on/off
failed.

Change-Id: I377ef95063eb82abf2a63ea8f8fce803ef45bcf6
Signed-off-by: Yuan-chang Hsieh <yuan-chang.hsieh@mediatek.corp-partner.google.com>

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Merge "refactor(cpus): export midr_match to a more global location" into integration

feat(s32g274ardb): use DDR reset deassertion

The DDR reset must be deasserted after
configuring AXI parity to guarantee the DDRC
registers are accessible for configuration
and PHY training.

Change-

feat(s32g274ardb): use DDR reset deassertion

The DDR reset must be deasserted after
configuring AXI parity to guarantee the DDRC
registers are accessible for configuration
and PHY training.

Change-Id: I80b8df9a7f0058941083893d4e7bb728768ae236
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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refactor(cpus): export midr_match to a more global location

It's a useful little helper that is horribly underused. Put it in common
code so that we can use it in future.

Change-Id: I635c581644b07a

refactor(cpus): export midr_match to a more global location

It's a useful little helper that is horribly underused. Put it in common
code so that we can use it in future.

Change-Id: I635c581644b07a6ca5ff68bb4fa475c4052da691
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "feat(rse): fix iovec parameter check in rse comms" into integration

feat(marvell): add odyssey platform header files

Add register files for marvell odyssey platform.

Change-Id: I09000f453303aca2a389c061d02c4151a5386f6b
Signed-off-by: Jaiprakash Singh <jaiprakashs@m

feat(marvell): add odyssey platform header files

Add register files for marvell odyssey platform.

Change-Id: I09000f453303aca2a389c061d02c4151a5386f6b
Signed-off-by: Jaiprakash Singh <jaiprakashs@marvell.com>

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feat(qemu): enable ENABLE_FEAT_RAS and ENABLE_FEAT_SB

Both are now FEAT_STATE_CHECKED enabled so they can be now be used.

Change-Id: I2485d583349e432014808a775ef57799eed4a596
Signed-off-by: Boyan K

feat(qemu): enable ENABLE_FEAT_RAS and ENABLE_FEAT_SB

Both are now FEAT_STATE_CHECKED enabled so they can be now be used.

Change-Id: I2485d583349e432014808a775ef57799eed4a596
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpufeat): update FEAT_SB's FEAT_STATE_CHECKED status

FEAT_SB is mostly FEAT_STATE_CHECKED enabled but that is not apparent
from docs and code's check is sub-optimal. Update docs to make this
ap

feat(cpufeat): update FEAT_SB's FEAT_STATE_CHECKED status

FEAT_SB is mostly FEAT_STATE_CHECKED enabled but that is not apparent
from docs and code's check is sub-optimal. Update docs to make this
apparent and update code to have a proper FEAT_STATE_CHECKED fallback.

Also enable it for FVP so it's tested a bit more.

Change-Id: I1374c4828b235ad16904f6c4ac9e39b9c2596a37
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpufeat): advertise support for FEAT_RASv2

From a PE architecture standpoint, FEAT_RASv2 only does three things:
* adds the SCR_EL3.TWERR trap bit (active high). That defaults to 0
unless RAS

feat(cpufeat): advertise support for FEAT_RASv2

From a PE architecture standpoint, FEAT_RASv2 only does three things:
* adds the SCR_EL3.TWERR trap bit (active high). That defaults to 0
unless RAS_TRAP_NS_ERR_REC_ACCESS overrides it but that's unused.
* adds the read only ERXGSR_EL1 register which cannot be saved/restored.
* changes the signalling of Uncontainable Instruction Aborts. When
FEAT_RASv2 is present Uncontainable EAs cannot happen and instead
SErrors will be signalled with more information.

So there isn't much to do and we can safely advertise FEAT_RASv2
support.

Change-Id: I07e29dbbd7fe824bed5a22ae22bd50eb16a0acd0
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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