fix(morello): dts: fix GICv3 compatible string

The official GICv3 DT bindings require only a limited number of
compatible string, and disavowes the naming of an implementation.
Linux' "make dtbs_che

fix(morello): dts: fix GICv3 compatible string

The official GICv3 DT bindings require only a limited number of
compatible string, and disavowes the naming of an implementation.
Linux' "make dtbs_check" reports:
============
.../morello-soc.dt.yaml: interrupt-controller@2c010000: compatible: 'oneOf' conditional failed, one must be fixed:
['arm,gic-600', 'arm,gic-v3'] is too long
'arm,gic-600' is not one of ['qcom,msm8996-gic-v3']
'arm,gic-v3' was expected
From schema: Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
============

Drop the redundant (because runtime detectable) and undocumented
implementation version, and just use the standard compatible string.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I05b207df271d6aa5bf3f2163f99ac0c594204c75

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fix(morello): dts: fix DT node naming

The various official DT bindings only allow certain node name patterns.
Linux' "make dtbs_check" reports:
===========
.../morello-soc.dt.yaml: sram@45200000: 's

fix(morello): dts: fix DT node naming

The various official DT bindings only allow certain node name patterns.
Linux' "make dtbs_check" reports:
===========
.../morello-soc.dt.yaml: sram@45200000: 'scp-shmem@0', 'scp-shmem@80' do not match any of the regexes: '^([a-z0-9]*-)?sram(-section)?@[a-f0-9]+$', 'pinctrl-[0-9]+'
From schema: Documentation/devicetree/bindings/sram/sram.yaml
.../morello-soc.dt.yaml: uart@2a400000: $nodename:0: 'uart@2a400000' does not match '^serial(@.*)?$'
From schema: Documentation/devicetree/bindings/serial/pl011.yaml
.../morello-soc.dt.yaml: interrupt-controller@2c010000: 'its@30040000', 'its@30060000', 'its@30080000', 'its@300a0000' do not match any of the regexes: '^(msi-controller|gic-its|interrupt-controller)@[0-9a-f]+$', '^gic-its@', '^interrupt-controller@[0-9a-f]+$', 'pinctrl-[0-9]+'
From schema: Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
===========

Rename the node names to improve bindings compliance.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ieff576512853eb2bf932c7a2b338c91e0c116b87

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fix(morello): dts: fix SCMI shmem/mboxes grouping

The official Arm MHU DT binding suggests to group the shmem (and mboxes)
values to signify the number of mailboxes supported.
Linux' "make dtbs_chec

fix(morello): dts: fix SCMI shmem/mboxes grouping

The official Arm MHU DT binding suggests to group the shmem (and mboxes)
values to signify the number of mailboxes supported.
Linux' "make dtbs_check" reports:
============
.../morello-soc.dt.yaml: scmi: shmem:0: [17, 18] is too long
From schema: dt-schema.git/dtschema/schemas/mbox/mbox-consumer.yaml
============

Add angle brackets at the right location to mark the boundaries between
the two mailbox instances used.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: If585c98b5e8e55cd5c0b1261e03ce4b91a4c0413

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fix(morello): dts: use documented DPU compatible string

The official Arm Komeda DPU DT binding only mentions the "arm,mali-d71"
string as a possible compatible string. The D32 version is just a
vari

fix(morello): dts: use documented DPU compatible string

The official Arm Komeda DPU DT binding only mentions the "arm,mali-d71"
string as a possible compatible string. The D32 version is just a
variant of the D71, and the revision can and will be auto-detected at
runtime.
Add the usual fallback compatible string scheme to contain a documented
compatible string.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ic1eade122b030dc983944b161eec175facf75357

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fix(morello): dts: fix DP SMMU IRQ ordering

The official SMMUv3 DT bindings require a certain order of the
interrupts, Linux' "make dtbs_check" reports:
============
.../morello-soc.dt.yaml: iommu@2

fix(morello): dts: fix DP SMMU IRQ ordering

The official SMMUv3 DT bindings require a certain order of the
interrupts, Linux' "make dtbs_check" reports:
============
.../morello-soc.dt.yaml: iommu@2ce00000: interrupt-names: 'oneOf' conditional failed, one must be fixed:
['eventq', 'cmdq-sync', 'gerror'] is too long
'combined' was expected
'gerror' was expected
'priq' was expected
'cmdq-sync' was expected
From schema: Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
============

Swap the order of the interrupts to improve bindings compliance.

Actually in this case the binding needs to be extended, since PRI is not
implemented in the SMMU in this case, so the PRI IRQ should be optional,
but we still want to describe the CMDQ sync IRQ. A patch for the binding
is pending.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I3978f1c087136cd4c2e8f7fd4d1bba5b95f72726

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fix(morello): dts: fix SMMU IRQ ordering

The official SMMUv3 DT bindings require a certain order of the
interrupts, Linux' "make dtbs_check" reports:
============
.../morello-soc.dt.yaml: iommu@4f40

fix(morello): dts: fix SMMU IRQ ordering

The official SMMUv3 DT bindings require a certain order of the
interrupts, Linux' "make dtbs_check" reports:
============
.../morello-soc.dt.yaml: iommu@4f400000: interrupt-names: 'oneOf' conditional failed, one must be fixed:
['eventq', 'priq', 'cmdq-sync', 'gerror'] is too long
'combined' was expected
'gerror' was expected
'priq' was expected
'cmdq-sync' was expected
From schema: Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
============

Swap the order of the interrupt-names and their corresponding interrupts
values to improve bindings compliance.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I2110b8509593a4f1aadff11bd518ec4a0f3f5d3c

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fix(morello): dts: add model names

The core root node DT bindings require every DT to have a "model"
property. Linux' "make dtbs_check" reports:
============
.../morello-soc.dt.yaml: /: 'model' is a

fix(morello): dts: add model names

The core root node DT bindings require every DT to have a "model"
property. Linux' "make dtbs_check" reports:
============
.../morello-soc.dt.yaml: /: 'model' is a required property
From schema: dt-schema.git/dtschema/schemas/root-node.yaml
============

Add a model name to both the SoC and FVP files to improve bindings
compliance.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I64923edb947f8939dfa24c13a37996b1ba34ea54

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Merge "fix(mt8186): move SSPM base register definition to platform_def.h" into integration

fix(mt8186): move SSPM base register definition to platform_def.h

- move base register definition to platform_def.h for maintenance.
- SSPM_MBOX_3_BASE is redefined, use SSPM_MBOX_BASE instead.

Sig

fix(mt8186): move SSPM base register definition to platform_def.h

- move base register definition to platform_def.h for maintenance.
- SSPM_MBOX_3_BASE is redefined, use SSPM_MBOX_BASE instead.

Signed-off-by: Yidi Lin <yidilin@chromium.org>
Change-Id: Ibb0291ce7b7426068392e90bd70f29d1a90d5297

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Merge "refactor(fvp): add missing header guard in fvp_critical_data.h" into integration

refactor(fvp): add missing header guard in fvp_critical_data.h

Change-Id: If7d1a9dd756164c8e31e29d9e36973f1a21fc8b6
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

Merge "docs(security): update info on use of OpenSSL 3.0" into integration

docs(security): update info on use of OpenSSL 3.0

OpenSSL 3.0 is a pre-requisite since v2.7 and can be installed
on the operating system by updating the previous version.
However, this may not be co

docs(security): update info on use of OpenSSL 3.0

OpenSSL 3.0 is a pre-requisite since v2.7 and can be installed
on the operating system by updating the previous version.
However, this may not be convenient for everyone, as some may
want to keep their previous versions of OpenSSL.

This update on the docs shows that there is an alternative to
install OpenSSL on the system by using a local build of
OpenSSL 3.0 and pointing both the build and run commands to
that build.

Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: Ib9ad9ee5c333f7b04e2747ae02433aa66e6397f3

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Merge "feat(tc): move start address for BL1 to 0x1000" into integration

feat(tc): move start address for BL1 to 0x1000

Locate BL1 at 0x1000 to compensate for the MCUBoot
header size.

Signed-off-by: Anders Dellien <anders.dellien@arm.com>
Change-Id: I30a5ccf8212786479bf

feat(tc): move start address for BL1 to 0x1000

Locate BL1 at 0x1000 to compensate for the MCUBoot
header size.

Signed-off-by: Anders Dellien <anders.dellien@arm.com>
Change-Id: I30a5ccf8212786479bff8286f3d0abb9dec4b7d0

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Merge "docs: re-parent BL2 platform hooks for measured boot" into integration

Merge "fix(errata): workaround for Cortex-A78C 2132064" into integration

fix(errata): workaround for Cortex-A78C 2132064

Cortex-A78C erratum 2132064 is a cat B erratum that applies to revisions
r0p1 and r0p2 and is still open.

This patch implements workaround option 2 t

fix(errata): workaround for Cortex-A78C 2132064

Cortex-A78C erratum 2132064 is a cat B erratum that applies to revisions
r0p1 and r0p2 and is still open.

This patch implements workaround option 2 that places the data
prefetcher in the most conservative mode to greatly reduce prefetches
by writing the following bits to the value indicated:
ecltr[7:6], PF_MODE = 2'b11

SDEN can be found here:
https://developer.arm.com/documentation/SDEN2004089/latest

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ica2561c1e257643c2482085447ef852fa62a1eb2

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docs: re-parent BL2 platform hooks for measured boot

bl2_plat_mboot_init/finish() functions documentation was incorrectly
hooked up to BL2U-specific section.

Change-Id: I758cb8142e992b0c85ee36d5671

docs: re-parent BL2 platform hooks for measured boot

bl2_plat_mboot_init/finish() functions documentation was incorrectly
hooked up to BL2U-specific section.

Change-Id: I758cb8142e992b0c85ee36d5671fc9ecd5bde29b
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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Merge "build(changelog): add stm32mp13 and stm32mp15 fdts scopes" into integration

Merge "fix(ufs): removes dp and run-stop polling loops" into integration

fix(ufs): removes dp and run-stop polling loops

These polling loops are not required according to the spec

Signed-off-by: anans <anans@google.com>
Change-Id: I50d832ba495f30cc7a0553c84e58b747d51e0a

fix(ufs): removes dp and run-stop polling loops

These polling loops are not required according to the spec

Signed-off-by: anans <anans@google.com>
Change-Id: I50d832ba495f30cc7a0553c84e58b747d51e0a4e

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feat(versal): get the handoff params using IPI

Use the IPI command GET_HANDOFF_PARAM to get the TF-A handoff
params, rather than using the PLM's PPU RAM area. With this
approach this resolves the is

feat(versal): get the handoff params using IPI

Use the IPI command GET_HANDOFF_PARAM to get the TF-A handoff
params, rather than using the PLM's PPU RAM area. With this
approach this resolves the issue when XPPU is enabled.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Change-Id: I6828c391ad696d2d36e994684aa21b023711ba2d

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refactor(xilinx): move the atf handoff structure

Move the ATF handoff structure from the plat_startup.c to the
header file plat_startup.h, as these can be used by the platform code.

Signed-off-by:

refactor(xilinx): move the atf handoff structure

Move the ATF handoff structure from the plat_startup.c to the
header file plat_startup.h, as these can be used by the platform code.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Change-Id: Ifb425d444eb65fe8648952d2ff64d4e92c2b340a

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refactor(versal): move payload and module ID macros

Move the payload and module ID macros from the pm_api_sys.c file and
add it in the header file, as these macros can be used other than PM.

Signe

refactor(versal): move payload and module ID macros

Move the payload and module ID macros from the pm_api_sys.c file and
add it in the header file, as these macros can be used other than PM.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Change-Id: I678444b79ac3799a82bd93915e4639b3babf5fb9

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