feat(pauth): add/modify helpers to support QARMA3

QARMA3 is a pointer authentication algorithm that generates
the PAC codes.

The is_armv8_3_pauth_present() helper was modified in order to
consider

feat(pauth): add/modify helpers to support QARMA3

QARMA3 is a pointer authentication algorithm that generates
the PAC codes.

The is_armv8_3_pauth_present() helper was modified in order to
consider the presence of the QARMA3 algorithm (i.e.: when
ID_AA64ISAR2_EL1.{GPA3, APA3} fields are not 0.

In addition, helper is_feat_pacqarma3_present() was implemented to
explicitly detect the presence of QARMA3 algorithm.

Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: I68e8fa7f8b7ca50d74ae0a2f5f182236d68f3d7b

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Merge "build: fix semantic ver generation for windows" into integration

Merge "fix(zynqmp): fix for incorrect afi write mask value" into integration

fix(zynqmp): fix for incorrect afi write mask value

Currently, the AFIFM6_WRCTRL bus-width configuration is not happening
correctly due to the wrong register write mask value. To fix this issue
upda

fix(zynqmp): fix for incorrect afi write mask value

Currently, the AFIFM6_WRCTRL bus-width configuration is not happening
correctly due to the wrong register write mask value. To fix this issue
updated the mask value handling logic.

Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Acked-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Change-Id: I8443c369a84339018310cfb6cd498d21474da3e4

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fix(errata): workaround for Cortex-A710 erratum 2147715

Cortex-A710 erratum 2147715 is a Cat B erratum that applies
to revision r2p0 of the CPU, and is fixed in r2p1. The work-
around is to set CPUA

fix(errata): workaround for Cortex-A710 erratum 2147715

Cortex-A710 erratum 2147715 is a Cat B erratum that applies
to revision r2p0 of the CPU, and is fixed in r2p1. The work-
around is to set CPUACTLR_EL1[22]=1. Setting this will cause
the CFP instruction to invalidate all branch predictor resources
regardless of the context.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest

Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: I94771bc1fc9b65a0c17d75200ec2b1df8a3279c6

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Merge "fix(lib/psa): update measured boot handle" into integration

feat(fvp/tsp_manifest): add example manifest for TSP

Add an example manifest for the EL3 SPMC on the FVP Platform
that allows booting the TSP example partition.

Signed-off-by: Marc Bonnici <marc.bo

feat(fvp/tsp_manifest): add example manifest for TSP

Add an example manifest for the EL3 SPMC on the FVP Platform
that allows booting the TSP example partition.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: Ie7f40328e0313abb5b1a121dfdc22a5f7387587f
Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>

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fix(spmc): fix relinquish validation check

The current implementation expects that the endpoint IDs of all
participants of a memory transaction to be listed in the relinquish
descriptor. As per the

fix(spmc): fix relinquish validation check

The current implementation expects that the endpoint IDs of all
participants of a memory transaction to be listed in the relinquish
descriptor. As per the FF-A spec, aside from the current partition
ID, only the IDs of stream endpoints whose behalf it is relinquishing
the memory region must be specified.

The current implementation does not currently support proxy endpoints
therefore ensure that the endpoint count is always equal to 1 and
no stream endpoint IDs are specified and instead just verify the
caller is a valid participant in the memory transaction.

Additionally reuse the updated check in the retrieve request flow
for additional verification.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I3b970196af8a16b2531607775398cb8a2473793b

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Merge changes from topic "stm32mp13-updates" into integration

* changes:
feat(stm32mp1): manage STM32MP13 rev.Y
feat(stm32mp13-fdts): use STM32MP_DDR_S_SIZE in fw-config
fix(stm32mp13-fdts): c

Merge changes from topic "stm32mp13-updates" into integration

* changes:
feat(stm32mp1): manage STM32MP13 rev.Y
feat(stm32mp13-fdts): use STM32MP_DDR_S_SIZE in fw-config
fix(stm32mp13-fdts): cleanup DT files
fix(stm32mp13-fdts): update SDMMC max frequency
fix(stm32mp13-fdts): align sdmmc pins with kernel

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Merge "feat(rng-trap): add EL3 support for FEAT_RNG_TRAP" into integration

feat(rng-trap): add EL3 support for FEAT_RNG_TRAP

FEAT_RNG_TRAP introduces support for EL3 trapping of reads of the
RNDR and RNDRRS registers, which is enabled by setting the
SCR_EL3.TRNDR bit. This

feat(rng-trap): add EL3 support for FEAT_RNG_TRAP

FEAT_RNG_TRAP introduces support for EL3 trapping of reads of the
RNDR and RNDRRS registers, which is enabled by setting the
SCR_EL3.TRNDR bit. This patch adds a new build flag
ENABLE_FEAT_RNG_TRAP that enables the feature.
This feature is supported only in AArch64 state from Armv8.5 onwards.

Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: Ia9f17aef3444d3822bf03809036a1f668c9f2d89

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Merge "fix(errata): workaround for Neoverse-N2 erratum 2376738" into integration

feat(stm32mp1): manage STM32MP13 rev.Y

The new SoC version for STM32MP13 is the revision Y. The register
SYSCFG_IDC is updated for this new version with the value 0x1003.
The function stm32mp_get_so

feat(stm32mp1): manage STM32MP13 rev.Y

The new SoC version for STM32MP13 is the revision Y. The register
SYSCFG_IDC is updated for this new version with the value 0x1003.
The function stm32mp_get_soc_name() should also be updated to manage
this new SoC revision.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I4f2fa5f1503f17db93d8413c79c2b7a18d279f9b

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feat(stm32mp13-fdts): use STM32MP_DDR_S_SIZE in fw-config

Align with STM32MP15 file, use the macro STM32MP_DDR_S_SIZE, instead of
an hard-coded value.

Signed-off-by: Yann Gautier <yann.gautier@st.c

feat(stm32mp13-fdts): use STM32MP_DDR_S_SIZE in fw-config

Align with STM32MP15 file, use the macro STM32MP_DDR_S_SIZE, instead of
an hard-coded value.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ib31bed1ffe89ff221fab1884a2db729ce1e21846

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fix(stm32mp13-fdts): cleanup DT files

Instead of adding all peripheral nodes in SoC DT files, and then
removing them with BL2 overlay file, just remove them from SoC files.
And remove peripherals th

fix(stm32mp13-fdts): cleanup DT files

Instead of adding all peripheral nodes in SoC DT files, and then
removing them with BL2 overlay file, just remove them from SoC files.
And remove peripherals that are not used in TF-A on STM32MP13.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I0c408d29b55cb94644c92539460fc62485781223

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fix(stm32mp13-fdts): update SDMMC max frequency

On STM32MP13, the max frequency for IOs is 130MHz, update the SDMMC
max-frequency property with this value. This is an alignment with
Linux DT file.

fix(stm32mp13-fdts): update SDMMC max frequency

On STM32MP13, the max frequency for IOs is 130MHz, update the SDMMC
max-frequency property with this value. This is an alignment with
Linux DT file.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: If4b364f53f87d4b5d276a976af486a3bf083f49b

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fix(stm32mp13-fdts): align sdmmc pins with kernel

Update the pinctrl nodes for sdmmc instances in stm32mp13-pinctrl.dtsi
file to align with Linux. The boards DT files then need to be updated
accordi

fix(stm32mp13-fdts): align sdmmc pins with kernel

Update the pinctrl nodes for sdmmc instances in stm32mp13-pinctrl.dtsi
file to align with Linux. The boards DT files then need to be updated
accordingly.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I4e1f3cf78794bfb7bbe53cfc7e88623c7e79855d

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Merge changes from topic "st-mmc-updates" into integration

* changes:
feat(st-sdmmc2): define FIFO size
feat(st-sdmmc2): make reset property optional
feat(st): enable MMC_FLAG_SD_CMD6 for SD-c

Merge changes from topic "st-mmc-updates" into integration

* changes:
feat(st-sdmmc2): define FIFO size
feat(st-sdmmc2): make reset property optional
feat(st): enable MMC_FLAG_SD_CMD6 for SD-cards
feat(st-sdmmc2): manage CMD6
feat(mmc): manage SD Switch Function for high speed mode

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Merge changes from topic "st-etzpc-cleanup" into integration

* changes:
refactor(stm32mp15-fdts): remove ETZPC status
refactor(st-drivers): do not rely on DT in etzpc_init

fix(errata): workaround for Neoverse-N2 erratum 2376738

Neoverse-N2 erratum 2376738 is a Cat B erratum that applies
to revision r0p0 of the CPU. It is fixed in r0p1. The workaround
is to set CPUACTL

fix(errata): workaround for Neoverse-N2 erratum 2376738

Neoverse-N2 erratum 2376738 is a Cat B erratum that applies
to revision r0p0 of the CPU. It is fixed in r0p1. The workaround
is to set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to
behave like PLD/PRFM LD and not cause invalidations to other
PE caches.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: I4ad4434f9b7210244e67046d9657d218857dced5

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feat(st-sdmmc2): define FIFO size

Instead of using hard-coded values in stm32_sdmmc2_read() function,
use a defined SDMMC_FIFO_SIZE, which is 64 on STM32MP1.

Signed-off-by: Yann Gautier <yann.gauti

feat(st-sdmmc2): define FIFO size

Instead of using hard-coded values in stm32_sdmmc2_read() function,
use a defined SDMMC_FIFO_SIZE, which is 64 on STM32MP1.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I1ace0a28fbddae474379f0187371b9c360ceb7b3

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feat(st-sdmmc2): make reset property optional

Although not recommended, the reset property could be made optional.
This way the driver will probe even if no reset property is provided
in an sdmmc no

feat(st-sdmmc2): make reset property optional

Although not recommended, the reset property could be made optional.
This way the driver will probe even if no reset property is provided
in an sdmmc node in DT. This reset is already optional in Linux.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I6e63ff00118d9497f505d6379982334dd62686ca

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feat(st): enable MMC_FLAG_SD_CMD6 for SD-cards

This flag allows switching to High-Speed mode on SD-cards.
The gain is ~44ms when using SP_min, and ~55ms with OP-TEE.

Change-Id: Ic396c6a14201580b5e5

feat(st): enable MMC_FLAG_SD_CMD6 for SD-cards

This flag allows switching to High-Speed mode on SD-cards.
The gain is ~44ms when using SP_min, and ~55ms with OP-TEE.

Change-Id: Ic396c6a14201580b5e5627e6174b85b437b87cae
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(st-sdmmc2): manage CMD6

For SD-cards, CMD6 is used to switch functions, like setting high speed
mode. As it has another meaning for eMMC, and may not work on standard
capacity SD-cards, it must

feat(st-sdmmc2): manage CMD6

For SD-cards, CMD6 is used to switch functions, like setting high speed
mode. As it has another meaning for eMMC, and may not work on standard
capacity SD-cards, it must be checked with MMC_IS_SD_HC flag.
As ACMD6 is also used, and will have the same index, a check on
CMD/ACMD commands is done: a boolean is stored depending on previous
command. It is set to true if CMD55 is issued, for other commands
it is set to false.

Change-Id: I6c2b9c7637656f858601ec075de1cb5f57af271a
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(mmc): manage SD Switch Function for high speed mode

On SD-cards, Switch Function Command (CMD6) is used to switch
functions, like setting High Speed mode. It is useful for high capacity
cards t

feat(mmc): manage SD Switch Function for high speed mode

On SD-cards, Switch Function Command (CMD6) is used to switch
functions, like setting High Speed mode. It is useful for high capacity
cards to double frequency (from 25MHz by default to 50MHz).
If the SD-card is High Capacity, a CMD6 is issued after filling the
device information. If High Speed mode is supported and the switch is
OK, then the max_bus_freq can be set to 50MHz. The driver set_ios()
function should then be called to update peripheral configuration,
especially clock prescaler.

Change-Id: I2d6807aa7f9440d2b2f907a747cd3b47a2ba1545
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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