fix(xilinx): update define for ZynqMP specific functions

Instead of exclude code for Versal, define only for ZynqMP.
For new platforms this code should be excluded so instead of
excluding for all pl

fix(xilinx): update define for ZynqMP specific functions

Instead of exclude code for Versal, define only for ZynqMP.
For new platforms this code should be excluded so instead of
excluding for all platform, define only for ZynqMP.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I45798dadc0f374c5794f517f7d0158675a75caa9

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fix(xilinx): remove unnecessary header include

Platform specific IPI header inclusion is not required
in common IPI source file. So remove inclusion of the same.

Signed-off-by: Rajan Vaja <rajan.va

fix(xilinx): remove unnecessary header include

Platform specific IPI header inclusion is not required
in common IPI source file. So remove inclusion of the same.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I6686757f00370c6ec42b5ee2c44ea5cd13da70c0

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fix(xilinx): include missing header

pm_ipi.h needs some definitions from stddef.h so include it.
Currently it is working because required file is included
indirectly due to other includes.

Signed-o

fix(xilinx): include missing header

pm_ipi.h needs some definitions from stddef.h so include it.
Currently it is working because required file is included
indirectly due to other includes.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Ic4a6c469c3152e21eaeb365ba96f3a29f14593bf

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chore(zynqmp): fix comment style in zynqmp_def.h

Add missing space in one line comment to follow common coding style.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Idebf8f34bf48444e

chore(zynqmp): fix comment style in zynqmp_def.h

Add missing space in one line comment to follow common coding style.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Idebf8f34bf48444ee20a68ac3e6fd7f5a41bf8b0

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chore(versal): add missing dot at the end of sentence

Add missing dot at the end of sentence.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I356e65fd8c572c12795e3492dd02d73f48cb4b67

fix(zynqmp): remove additional 0x in %p print

%p is already printing value in hex that's why 0x prefix is not needed.
Origin message looks like this
"NOTICE: Can't read DT at 0x0x100000"
and after

fix(zynqmp): remove additional 0x in %p print

%p is already printing value in hex that's why 0x prefix is not needed.
Origin message looks like this
"NOTICE: Can't read DT at 0x0x100000"
and after fixing
"NOTICE: Can't read DT at 0x100000"

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: If83c485a61441f6105d8cbd797f04060dfce2817

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fix(versal): fix Misra-C violations in bl31_setup and pm_svc_main

Fix some Misra-C violations. The similar fixes were done by commit
eb0d2b17722c ("fix(zynqmp): resolve misra R15.6 warnings") and co

fix(versal): fix Misra-C violations in bl31_setup and pm_svc_main

Fix some Misra-C violations. The similar fixes were done by commit
eb0d2b17722c ("fix(zynqmp): resolve misra R15.6 warnings") and commit
dd1fe7178b57 ("fix(zynqmp): resolve misra R14.4 warnings").

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I3ffa92724a09871f7f99c9ac6c326994c165e9bd

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Merge "fix(zynqmp): ensure memory write finish with dsb()" into integration

Merge "fix(cpus): workaround for Cortex-A710 2216384" into integration

fix(zynqmp): ensure memory write finish with dsb()

GICD reg write must complete before core goes to idle
mode. Achieve this with dsb() barrier instruction in IPI
ISR

Signed-off-by: Tanmay Shah <tan

fix(zynqmp): ensure memory write finish with dsb()

GICD reg write must complete before core goes to idle
mode. Achieve this with dsb() barrier instruction in IPI
ISR

Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Change-Id: I5af42ca901567ee5e54a5434ebe3e673a92cb9be

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docs(build): update GCC to 11.3.Rel1 version

This toolchain provides multiple cross compilers and is publicly
available on https://developer.arm.com/

We build TF-A in CI using:
AArch32 bare-metal t

docs(build): update GCC to 11.3.Rel1 version

This toolchain provides multiple cross compilers and is publicly
available on https://developer.arm.com/

We build TF-A in CI using:
AArch32 bare-metal target (arm-none-eabi)
AArch64 ELF bare-metal target (aarch64-none-elf)

Change-Id: I94e13f6c1ebe3a4a58ca6c79c1605bd300b372d3
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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fix(zynqmp): move debug bl31 based address back to OCM

The commit 389594dfa7e6 ("fix(zynqmp): move bl31 with DEBUG=1 back to OCM")
tried to move address to OCM but address was actually out of OCM an

fix(zynqmp): move debug bl31 based address back to OCM

The commit 389594dfa7e6 ("fix(zynqmp): move bl31 with DEBUG=1 back to OCM")
tried to move address to OCM but address was actually out of OCM and likely
it was typo. Correct default address should be 0xfffe5000. If TF-A size is
bigger please select location DDR which should be fine for DEBUG cases.

Reported-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I055f3a59cdca527f6029fcc2a19d76be35924d24

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feat(versal): update macro name to generic and move to common place

Update TZ_VERSION macro name to generic macro name and move to
common header file so that it can be used for keystoneb.

Signed-of

feat(versal): update macro name to generic and move to common place

Update TZ_VERSION macro name to generic macro name and move to
common header file so that it can be used for keystoneb.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@xilinx.com>
Acked-by: Tanmay Shah <tanmay.shah@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Ic3819eea78b6c7b51ffaa13081026dd191b76125

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Merge changes Id49d94f6,I35316310 into integration

* changes:
feat(versal): add infrastructure to handle multiple interrupts
fix(versal): add SGI register call version check

Merge "docs(porting-guide): correct typo of "bits" to "bytes"" into integration

feat(versal): add infrastructure to handle multiple interrupts

Only one hardcode interrupt handler is supported as of now.
This is IPI interrupt between APU and PMC processor.
This patch adds infras

feat(versal): add infrastructure to handle multiple interrupts

Only one hardcode interrupt handler is supported as of now.
This is IPI interrupt between APU and PMC processor.
This patch adds infrastructure to register multiple interrupt
handlers. This infrastructure was used and tested for two
interrupts and so, interrupt id and handler container size is
2 which is defined by MAX_INTR_EL3. Interrupt id is not used
as container index due to size constraints. User is expected to
adjust MAX_INTR_EL3 based on how many interrupts are handled in
TF-A

Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Change-Id: Id49d94f6773fbb6874ccf89c0d12572efc7e678e

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fix(versal): add SGI register call version check

PM_FEATURE_CHECK is supported only for platform
management API. PM_LOAD_PDI command is not intended
for platform management. This patch removes versi

fix(versal): add SGI register call version check

PM_FEATURE_CHECK is supported only for platform
management API. PM_LOAD_PDI command is not intended
for platform management. This patch removes version
check of PM_LOAD_PDI and adds version check of command
that is used for SGI registartion.

Signed-off-by: Tanmay Shah <tanmay.shah@xilinx.com>
Change-Id: I353163109b639acab73120f405a811770e8831a0

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Merge "chore: use tabs for indentation" into integration

chore: use tabs for indentation

This patch changes the definition of image_info_t to follow the TF-A
coding style documented at
https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-styl

chore: use tabs for indentation

This patch changes the definition of image_info_t to follow the TF-A
coding style documented at
https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-style.html

Signed-off-by: Jorge Troncoso <jatron@google.com>
Change-Id: I17af22b4ba60b41cf0b5fa84ac47beeb1536edcc

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docs(porting-guide): correct typo of "bits" to "bytes"

The CACHE_WRITEBACK_GRANULE is documented to be in bits, but
specifying the value in bits broke a build. Further investigation
suggests that th

docs(porting-guide): correct typo of "bits" to "bytes"

The CACHE_WRITEBACK_GRANULE is documented to be in bits, but
specifying the value in bits broke a build. Further investigation
suggests that the value should in fact be in bytes. See
https://github.com/ARM-software/arm-trusted-firmware/blob/master/include/arch/aarch64/
smccc_helpers.h#L101
and
https://gcc.gnu.org/onlinedocs/gcc-12.2.0/gcc/Common-Type-Attributes.html

Change-Id: I9a2b2fbe18d5a58a8f9aeb2726a0623f3484c88e
Signed-off-by: Max Yu <maxlyu@google.com>

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Merge "fix(mmc): resolve the build error" into integration

fix(mmc): resolve the build error

Adding the header file plat/common/common_def.h to
resolve the "SIZE_128" undeclared identifier error.

Change-Id: I399edf4248776f6dd9f93e000b8672cadc71509d
Signed-

fix(mmc): resolve the build error

Adding the header file plat/common/common_def.h to
resolve the "SIZE_128" undeclared identifier error.

Change-Id: I399edf4248776f6dd9f93e000b8672cadc71509d
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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Merge changes from topic "fix_fip_in_emmc_boot" into integration

* changes:
fix(st): add max size for FIP in eMMC boot part
feat(mmc): get boot partition size

Merge "fix(cpus): workaround for Cortex-A78C erratum 2376749" into integration

fix(cpus): workaround for Cortex-A78C erratum 2376749

Cortex-A78C erratum 2376749 is a Cat B erratum that applies
to revisions r0p1 and r0p2 of the A78C and is currently open.
The workaround is to s

fix(cpus): workaround for Cortex-A78C erratum 2376749

Cortex-A78C erratum 2376749 is a Cat B erratum that applies
to revisions r0p1 and r0p2 of the A78C and is currently open.
The workaround is to set CPUACTLR2_EL1[0] to 1 to force
PLDW/PFRM ST to behave like PLD/PRFM LD and not cause
invalidations to other PE caches.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN2004089/latest

Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: I3b29f4b7f167bf499d5d11ffef91a94861bd1383

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