1 /* 2 * Copyright 2020-2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <context.h> 14 #include <drivers/arm/tzc380.h> 15 #include <drivers/console.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <lib/el3_runtime/context_mgmt.h> 18 #include <lib/mmio.h> 19 #include <lib/xlat_tables/xlat_tables_v2.h> 20 #include <plat/common/platform.h> 21 22 #include <dram.h> 23 #include <gpc.h> 24 #include <imx_aipstz.h> 25 #include <imx_uart.h> 26 #include <imx_rdc.h> 27 #include <imx8m_caam.h> 28 #include <imx8m_csu.h> 29 #include <platform_def.h> 30 #include <plat_imx8.h> 31 32 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 33 34 static const mmap_region_t imx_mmap[] = { 35 GIC_MAP, AIPS_MAP, OCRAM_S_MAP, DDRC_MAP, 36 NOC_MAP, {0}, 37 }; 38 39 static const struct aipstz_cfg aipstz[] = { 40 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 41 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 42 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 43 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 44 {0}, 45 }; 46 47 static const struct imx_rdc_cfg rdc[] = { 48 /* Master domain assignment */ 49 RDC_MDAn(RDC_MDA_M7, DID1), 50 51 /* peripherals domain permission */ 52 RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), 53 54 /* memory region */ 55 56 /* Sentinel */ 57 {0}, 58 }; 59 60 static const struct imx_csu_cfg csu_cfg[] = { 61 /* peripherals csl setting */ 62 CSU_CSLx(CSU_CSL_OCRAM, CSU_SEC_LEVEL_2, UNLOCKED), 63 CSU_CSLx(CSU_CSL_OCRAM_S, CSU_SEC_LEVEL_2, UNLOCKED), 64 65 /* master HP0~1 */ 66 67 /* SA setting */ 68 69 /* HP control setting */ 70 71 /* Sentinel */ 72 {0} 73 }; 74 75 static entry_point_info_t bl32_image_ep_info; 76 static entry_point_info_t bl33_image_ep_info; 77 78 /* get SPSR for BL33 entry */ 79 static uint32_t get_spsr_for_bl33_entry(void) 80 { 81 unsigned long el_status; 82 unsigned long mode; 83 uint32_t spsr; 84 85 /* figure out what mode we enter the non-secure world */ 86 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 87 el_status &= ID_AA64PFR0_ELX_MASK; 88 89 mode = (el_status) ? MODE_EL2 : MODE_EL1; 90 91 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 92 return spsr; 93 } 94 95 static void bl31_tzc380_setup(void) 96 { 97 unsigned int val; 98 99 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28); 100 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 101 return; 102 103 tzc380_init(IMX_TZASC_BASE); 104 105 /* 106 * Need to substact offset 0x40000000 from CPU address when 107 * programming tzasc region for i.mx8mp. 108 */ 109 110 /* Enable 1G-5G S/NS RW */ 111 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 112 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 113 } 114 115 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 116 u_register_t arg2, u_register_t arg3) 117 { 118 static console_t console; 119 unsigned int val; 120 unsigned int i; 121 122 /* Enable CSU NS access permission */ 123 for (i = 0; i < 64; i++) { 124 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff); 125 } 126 127 imx_aipstz_init(aipstz); 128 129 imx_rdc_init(rdc); 130 131 imx_csu_init(csu_cfg); 132 133 /* config the ocram memory range for secure access */ 134 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, 0x4E1); 135 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c); 136 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000); 137 138 console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 139 IMX_CONSOLE_BAUDRATE, &console); 140 /* This console is only used for boot stage */ 141 console_set_scope(&console, CONSOLE_FLAG_BOOT); 142 143 imx8m_caam_init(); 144 145 /* 146 * tell BL3-1 where the non-secure software image is located 147 * and the entry state information. 148 */ 149 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 150 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 151 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 152 153 #if defined(SPD_opteed) || defined(SPD_trusty) 154 /* Populate entry point information for BL32 */ 155 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 156 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 157 bl32_image_ep_info.pc = BL32_BASE; 158 bl32_image_ep_info.spsr = 0; 159 160 /* Pass TEE base and size to bl33 */ 161 bl33_image_ep_info.args.arg1 = BL32_BASE; 162 bl33_image_ep_info.args.arg2 = BL32_SIZE; 163 164 #ifdef SPD_trusty 165 bl32_image_ep_info.args.arg0 = BL32_SIZE; 166 bl32_image_ep_info.args.arg1 = BL32_BASE; 167 #else 168 /* Make sure memory is clean */ 169 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0); 170 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 171 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 172 #endif 173 #endif 174 175 bl31_tzc380_setup(); 176 } 177 178 #define MAP_BL31_TOTAL \ 179 MAP_REGION_FLAT(BL31_BASE, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE) 180 #define MAP_BL31_RO \ 181 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE) 182 #define MAP_COHERENT_MEM \ 183 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ 184 MT_DEVICE | MT_RW | MT_SECURE) 185 #define MAP_BL32_TOTAL \ 186 MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW) 187 188 void bl31_plat_arch_setup(void) 189 { 190 const mmap_region_t bl_regions[] = { 191 MAP_BL31_TOTAL, 192 MAP_BL31_RO, 193 #if USE_COHERENT_MEM 194 MAP_COHERENT_MEM, 195 #endif 196 /* Map TEE memory */ 197 MAP_BL32_TOTAL, 198 {0} 199 }; 200 201 setup_page_tables(bl_regions, imx_mmap); 202 enable_mmu_el3(0); 203 } 204 205 void bl31_platform_setup(void) 206 { 207 generic_delay_timer_init(); 208 209 /* select the CKIL source to 32K OSC */ 210 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1); 211 212 /* Init the dram info */ 213 dram_info_init(SAVED_DRAM_TIMING_BASE); 214 215 plat_gic_driver_init(); 216 plat_gic_init(); 217 218 imx_gpc_init(); 219 } 220 221 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 222 { 223 if (type == NON_SECURE) { 224 return &bl33_image_ep_info; 225 } 226 227 if (type == SECURE) { 228 return &bl32_image_ep_info; 229 } 230 231 return NULL; 232 } 233 234 unsigned int plat_get_syscnt_freq2(void) 235 { 236 return COUNTER_FREQUENCY; 237 } 238 239 #ifdef SPD_trusty 240 void plat_trusty_set_boot_args(aapcs64_params_t *args) 241 { 242 args->arg0 = BL32_SIZE; 243 args->arg1 = BL32_BASE; 244 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 245 } 246 #endif 247