docs(fwu): update firmware update design

Refactored legacy firmware design and added details about PSA
firmware updates.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I9c123

docs(fwu): update firmware update design

Refactored legacy firmware design and added details about PSA
firmware updates.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I9c123b3f62580d4271dbaff0a728b6412fae7890

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feat(zynqmp): add support for ProvenCore

ProvenCore requires secure SGIs to be handled at S-EL1. This patch
overrides the default ZynqMP configuration to handle them at EL3 in case
ProvenCore SPD is

feat(zynqmp): add support for ProvenCore

ProvenCore requires secure SGIs to be handled at S-EL1. This patch
overrides the default ZynqMP configuration to handle them at EL3 in case
ProvenCore SPD is enabled.

Signed-off-by: Jeremie Corbier <jeremie.corbier@provenrun.com>
Signed-off-by: Mélanie Favre <melanie.favre@provenrun.com>
Change-Id: I2e36d2983f82fbb9b7acf7e18791b8ed92811b60

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feat(services): add a SPD for ProvenCore

Adds a dispatcher for ProvenCore based on the test secure payload
dispatcher.

Signed-off-by: Florian Lugou <florian.lugou@provenrun.com>
Change-Id: I978afc3

feat(services): add a SPD for ProvenCore

Adds a dispatcher for ProvenCore based on the test secure payload
dispatcher.

Signed-off-by: Florian Lugou <florian.lugou@provenrun.com>
Change-Id: I978afc3af6a6f65791655685a7bc80070673c9f3

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fix(intel): fix asynchronous read response by copying data to input buffer

To fix that response should not be NULL when there is response data
need to be sent to input buffer by SDM.

Signed-off-by:

fix(intel): fix asynchronous read response by copying data to input buffer

To fix that response should not be NULL when there is response data
need to be sent to input buffer by SDM.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Id70289521792f5f995456d2e67e18f0185ca3fc0

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fix(intel): fix Mac verify update and finalize for return response data

To fix that the response data is returned when the source size ready
is still fit for response data size.

Signed-off-by: Sieu

fix(intel): fix Mac verify update and finalize for return response data

To fix that the response data is returned when the source size ready
is still fit for response data size.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Id8924137a5c33888e7042e9ab0e0e8c49b4a41ed

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feat(sgi): enable css implementation of warm reset

Enable the CSS implementation of the warm reset for the rdn2 platform.

In addition to these changes, fix coding style issues that are not
directl

feat(sgi): enable css implementation of warm reset

Enable the CSS implementation of the warm reset for the rdn2 platform.

In addition to these changes, fix coding style issues that are not
directly related to the code being introduced in this patch.

Change-Id: I75128d8bbcccbc26cf1e904691c7ef71349c622f
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>

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feat(scmi): send powerdown request to online secondary cpus

To initiate a reset or reboot, the nonsecure OS invokes the PSCI
SYSTEM_RESET function from any one core. As per the PSCI specification,
i

feat(scmi): send powerdown request to online secondary cpus

To initiate a reset or reboot, the nonsecure OS invokes the PSCI
SYSTEM_RESET function from any one core. As per the PSCI specification,
it is the responsibility of firmware to implement the system view of
the reset or reboot operation. For the platforms supported by CSS,
trigger the reset/reboot operation by sending an SGI to rest all CPUs
which are online. The CPUs respond to this interrupt by initiating its
powerdown sequence.

In addition to these changes, fix coding style issues that are not
directly related to the code being introduced in this patch.

Change-Id: I547253ee28ef7eefa78180d016893671a406bbfa
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>

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feat(plat/arm/css): add interrupt handler for reboot request

Add platform specific interrupt handler for handling the reboot of
all CPU's. On shutdown/reboot, only one CPU invoke PSCI and enter into

feat(plat/arm/css): add interrupt handler for reboot request

Add platform specific interrupt handler for handling the reboot of
all CPU's. On shutdown/reboot, only one CPU invoke PSCI and enter into
trusted firmware. The CPU which entered trusted firmware signals the
rest of the cores which are online using SGI to initiate power down
sequence. On receiving the SGI, the handler will power down the
GIC redistributor interface of the respective core, configure the power
control register and power down the CPU by executing wfi.

In addition to these changes, fix coding style issues that are not
directly related to the code being introduced in this patch.

Change-Id: I4917dfdc47be5ce7367bee629486a6344cdd706f
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>

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refactor(psci): move psci_do_pwrdown_sequence() out of private header

Move the psci_do_pwrdown_sequence() function declaration from PSCI
private header to common header. The psci_do_pwrdown_sequence

refactor(psci): move psci_do_pwrdown_sequence() out of private header

Move the psci_do_pwrdown_sequence() function declaration from PSCI
private header to common header. The psci_do_pwrdown_sequence is
required to support warm reset, where each CPU need to execute the
powerdown sequence.

Change-Id: I298e7a120be814941fa91c0b001002a080e56263
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>

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feat(plat/arm/css): add per-cpu power down support for warm reset

Add a new function to setup a SGI interrupt that will be used to trigger
a request for per-cpu power down when executing the PSCI SY

feat(plat/arm/css): add per-cpu power down support for warm reset

Add a new function to setup a SGI interrupt that will be used to trigger
a request for per-cpu power down when executing the PSCI SYSTEM_RESET
request. This will be used on CSS platform that require all the CPUs to
execute the CPU specific power down sequence to complete a warm reboot
sequence in which only the CPUs are power cycled.

Change-Id: I80da0f6c3cd0c5c442c82239ba1e1f773821a7f5
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>

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feat(scmi): set warm reboot entry point

Before issuing the system power down command, set the trusted mailbox
to 0. This will ensure that in the case of a warm/cold reset, the
primary CPU executes f

feat(scmi): set warm reboot entry point

Before issuing the system power down command, set the trusted mailbox
to 0. This will ensure that in the case of a warm/cold reset, the
primary CPU executes from the cold boot sequence, clearing any stale
jump address at this location.

Change-Id: I491ef5baf7a6728acd7e90e4558939ba77b8f9bf
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>

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fix(gicv3): update the affinity mask to 8 bit

The GIC ICC_SGI0R_EL1 register's affinity fields are 8bit wide for GIC
v3 and v4. Fix the SGIR_AFF_MASK variable accordingly.

Change-Id: I09f3fdd006708

fix(gicv3): update the affinity mask to 8 bit

The GIC ICC_SGI0R_EL1 register's affinity fields are 8bit wide for GIC
v3 and v4. Fix the SGIR_AFF_MASK variable accordingly.

Change-Id: I09f3fdd006708b40162776620f82abcfc6c3f782
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>

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Merge "fix: 'sp_mk_generator.py' reference to undef var" into integration

feat(tc): add RTC PL031 device tree node

It enables RTC PL031 driver in kernel.

Signed-off-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Change-Id: I6d7c1a5b6ce11b3d594f7575a747e72826c8d9b8

Merge "feat(gicv3): validate multichip data for GIC-700" into integration

Merge "fix(context mgmt): remove explicit ICC_SRE_EL2 register read" into integration

Merge "fix(versal): route GIC IPI interrupts during setup" into integration

Merge "fix(zynqmp): move debug bl31 based address back to OCM" into integration

fix(versal): route GIC IPI interrupts during setup

If primary core is down, then IPI interrupt should be
routed to another core for processing.

Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Chan

fix(versal): route GIC IPI interrupts during setup

If primary core is down, then IPI interrupt should be
routed to another core for processing.

Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Change-Id: I01d7c4232a18c0c3b3f3f9ddadfa6ff5bd2f2471

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fix: 'sp_mk_generator.py' reference to undef var

The script 'sp_mk_generator.py' was reworked in [1]. There was a
reference the variable 'data' left. This variable 'data' used to refer
to the json d

fix: 'sp_mk_generator.py' reference to undef var

The script 'sp_mk_generator.py' was reworked in [1]. There was a
reference the variable 'data' left. This variable 'data' used to refer
to the json data of a the sp layout file.
This patch fixed the reference with the proper variable according to the
rework [1].

[1] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=a96a07bfb66b7d38fe3da824e8ba183967659008

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I9ddbfa8d55a114bcef6997920522571e070fc7d2

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feat(gic): add APIs to raise NS and S-EL1 SGIs

This patch adds two helper functions:
- plat_ic_raise_ns_sgi to raise a NS SGI
- plat_ic_raise_s_el1_sgi to raise a S-EL1 SGI

Signed-off-by: Florian

feat(gic): add APIs to raise NS and S-EL1 SGIs

This patch adds two helper functions:
- plat_ic_raise_ns_sgi to raise a NS SGI
- plat_ic_raise_s_el1_sgi to raise a S-EL1 SGI

Signed-off-by: Florian Lugou <florian.lugou@provenrun.com>
Change-Id: I6f262dd1da1d77fec3f850eb74189e726b8e24da

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fix(context mgmt): remove explicit ICC_SRE_EL2 register read

ICC_SRE_EL2 has only 4 bits, while others are RES0. The library programs
all four of them already, so there is no need to read the previo

fix(context mgmt): remove explicit ICC_SRE_EL2 register read

ICC_SRE_EL2 has only 4 bits, while others are RES0. The library programs
all four of them already, so there is no need to read the previous
settings from the actual register.

This patch removes the explicit register read as a result.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Iff0cb3b0d6fd85e5ae891068e440d855973a1c5e

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Merge changes from topic "morello-dt-fix" into integration

* changes:
fix(morello): dts: remove #a-c and #s-c from memory node
fix(morello): dts: fix GICv3 compatible string
fix(morello): dts:

Merge changes from topic "morello-dt-fix" into integration

* changes:
fix(morello): dts: remove #a-c and #s-c from memory node
fix(morello): dts: fix GICv3 compatible string
fix(morello): dts: fix DT node naming
fix(morello): dts: fix SCMI shmem/mboxes grouping
fix(morello): dts: use documented DPU compatible string
fix(morello): dts: fix DP SMMU IRQ ordering
fix(morello): dts: fix SMMU IRQ ordering
fix(morello): dts: add model names
fix(morello): dts: fix stdout-path target

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Merge changes from topic "xilinx-pm-misc-changes" into integration

* changes:
fix(xilinx): update define for ZynqMP specific functions
fix(xilinx): remove unnecessary header include
fix(xilinx

Merge changes from topic "xilinx-pm-misc-changes" into integration

* changes:
fix(xilinx): update define for ZynqMP specific functions
fix(xilinx): remove unnecessary header include
fix(xilinx): include missing header

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Merge changes from topic "xilinx-misc-changes" into integration

* changes:
chore(zynqmp): fix comment style in zynqmp_def.h
chore(versal): add missing dot at the end of sentence
fix(zynqmp): r

Merge changes from topic "xilinx-misc-changes" into integration

* changes:
chore(zynqmp): fix comment style in zynqmp_def.h
chore(versal): add missing dot at the end of sentence
fix(zynqmp): remove additional 0x in %p print
fix(versal): fix Misra-C violations in bl31_setup and pm_svc_main

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