feat(fvp): increase BL31's stack size for DRTM support

The stack size of BL31 has been increased to accommodate the
introduction of mbedTLS support for DRTM.

Signed-off-by: Manish V Badarkhe <manis

feat(fvp): increase BL31's stack size for DRTM support

The stack size of BL31 has been increased to accommodate the
introduction of mbedTLS support for DRTM.

Signed-off-by: Manish V Badarkhe <manish.badarkhe@arm.com>
Signed-off-by: Lucian Paul-Trifu <lucian.paultrifu@gmail.com>
Change-Id: Id0beacf4df553af4ecbe714af20e71604ccfed59

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feat(fvp): add platform hooks for DRTM DMA protection

Added necessary platform hooks for DRTM DMA protection.
These calls will be used by the subsequent DRTM implementation
patches.
DRTM platform AP

feat(fvp): add platform hooks for DRTM DMA protection

Added necessary platform hooks for DRTM DMA protection.
These calls will be used by the subsequent DRTM implementation
patches.
DRTM platform API declarations have been listed down in a
separate header file.

Signed-off-by: Manish V Badarkhe <manish.badarkhe@arm.com>
Signed-off-by: Lucian Paul-Trifu <lucian.paultrifu@gmail.com>
Change-Id: Ib9726d1d3570800241bde702ee7006a64f1739ec

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build: forbid `ENABLE_RME=1` when `SEPARATE_CODE_AND_RODATA=0`

This change mitigates against read-only data being used for malicious
execution on platforms utilizing the RME/CCA.

Change-Id: I006853

build: forbid `ENABLE_RME=1` when `SEPARATE_CODE_AND_RODATA=0`

This change mitigates against read-only data being used for malicious
execution on platforms utilizing the RME/CCA.

Change-Id: I0068535aeaa5d2515c7c54ee0dc19200c7a86ba5
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge "fix(qemu): enable SVE and SME" into integration

Merge "fix(rss): fix build issues with comms protocol" into integration

fix(rss): fix build issues with comms protocol

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I77d2d3c5ac39a840b768f84f859d76b3965749aa

Merge changes from topic "mt8188 cpu_pm" into integration

* changes:
feat(mediatek): move lpm drivers back to common
feat(mt8188): add cpu_pm driver
fix(mt8188): refine c-state power domain fo

Merge changes from topic "mt8188 cpu_pm" into integration

* changes:
feat(mediatek): move lpm drivers back to common
feat(mt8188): add cpu_pm driver
fix(mt8188): refine c-state power domain for extensibility

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Merge "fix(mt8186-emi-mpu): fix SCP permission" into integration

fix: backtrace stack unwind misses lr adjustment

When pointer authentication is used the frame record return address
includes the pointer authentication code hence it must be masked out
when willing

fix: backtrace stack unwind misses lr adjustment

When pointer authentication is used the frame record return address
includes the pointer authentication code hence it must be masked out
when willing to compare the pointer value with another address or
checking its validity. The stack unwind function missed one case of
adjusting the return address leading to a misinterpreted corrupted stack
frame error message.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I435140937d5fd0f43da27c77d96056b7606d87e9

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fix(qemu): enable SVE and SME

Starting with QEMU v3.1.0 (Dec 2018), QEMU's TCG emulation engine supports
the SVE architecture extension. In QEMU v7.1.0 (Aug 2022) it also gained
SME support.

As it

fix(qemu): enable SVE and SME

Starting with QEMU v3.1.0 (Dec 2018), QEMU's TCG emulation engine supports
the SVE architecture extension. In QEMU v7.1.0 (Aug 2022) it also gained
SME support.

As it stands today, running TF-A under QEMU with "-cpu max" makes Linux
hang, because SME and SVE accesses trap to EL3, but are never handled
there. This is because the Linux kernel sees the SVE or SME feature bits,
and assumes firmware has enabled the feature for lower exception levels.
This requirement is described in the Linux kernel booting protocol.

Enable those features in the TF-A build, so that BL31 does the proper
EL3 setup to make the feature usable in non-secure world.
We check the actual feature bits before accessing SVE or SME registers,
so this is safe even for older QEMU version or when not running with
-cpu max. As SVE and SME are AArch64 features only, do not enable them
when building for AArch32.

Change-Id: I5b718eb298a0bbcf36244479e8d42e54a2faca61
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge changes from topic "aarch32_debug_aborts" into integration

* changes:
feat(stm32mp1): add plat_report_*_abort functions
feat(debug): add helpers for aborts on AARCH32
feat(debug): add AA

Merge changes from topic "aarch32_debug_aborts" into integration

* changes:
feat(stm32mp1): add plat_report_*_abort functions
feat(debug): add helpers for aborts on AARCH32
feat(debug): add AARCH32 CP15 fault registers

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Merge "feat(fvp): support building RSS comms driver" into integration

Merge "refactor(console): move putchar() to console driver" into integration

fix(mt8186-emi-mpu): fix SCP permission

Hardware video decoding is not working after enabling EMI MPU protection
for SCP.

According to coreboot DEVAPC setting, SCP belongs to domain 4 instead of
do

fix(mt8186-emi-mpu): fix SCP permission

Hardware video decoding is not working after enabling EMI MPU protection
for SCP.

According to coreboot DEVAPC setting, SCP belongs to domain 4 instead of
domain 3. So correct the permission setting.

BUG=b:249954378
TEST=play video and see codec irq count is incrementing.

Signed-off-by: Yidi Lin <yidilin@chromium.org>
Change-Id: If71de3eabf8682909f96924c159aa92f25deb96c

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feat(ethos-n)!: add support for SMMU streams

The Arm(R) Ethos(TM)-N NPU driver now supports configuring the SMMU
streams that the NPU shall use and will therefore no longer delegate
access to these

feat(ethos-n)!: add support for SMMU streams

The Arm(R) Ethos(TM)-N NPU driver now supports configuring the SMMU
streams that the NPU shall use and will therefore no longer delegate
access to these registers to the non-secure world. In order for the
driver to support this, the device tree parsing has been updated to
support parsing the allocators used by the NPU and what SMMU stream that
is associated with each allocator.

To keep track of what NPU device each allocator is associated with, the
resulting config from the device tree parsing will now group the NPU
cores and allocators into their respective NPU device.

The SMC API has been changed to allow the caller to specify what
allocator the NPU shall be configured to use and the API version has
been bumped to indicate this change.

Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I6ac43819133138614e3f55a014e93466fe3d5277

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Merge "fix(versal-net): use api_id directly without FUNCID_MASK" into integration

Merge changes I134f125f,Ia4bf45bf into integration

* changes:
refactor(sgi): rename RD-Edmunds to RD-V2
refactor(cpu): use the updated IP name for Demeter CPU

refactor(console): move putchar() to console driver

Moving putchar() out of libc and adding a weak dummy
implementation in libc.

This is to remove libc's dependencies to the platform
driver.

Signe

refactor(console): move putchar() to console driver

Moving putchar() out of libc and adding a weak dummy
implementation in libc.

This is to remove libc's dependencies to the platform
driver.

Signed-off-by: Claus Pedersen <claustbp@google.com>
Change-Id: Ib7fefaec0babb783def614ea23521f482fa4a28a

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feat(mediatek): move lpm drivers back to common

In order to sync drivers with MediaTek internal code base, we move lpm
drivers back to common folder.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediat

feat(mediatek): move lpm drivers back to common

In order to sync drivers with MediaTek internal code base, we move lpm
drivers back to common folder.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I1066e092febe0abb9782a46f668613e137737c88

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feat(mt8188): add cpu_pm driver

- Add cpu_pm driver for CPU idle and SMP flow.
- Add SMP driver for CPU power on/off control.
- Add CPC driver to handle CPU powered on/off in CPU suspend.
- Add mbox

feat(mt8188): add cpu_pm driver

- Add cpu_pm driver for CPU idle and SMP flow.
- Add SMP driver for CPU power on/off control.
- Add CPC driver to handle CPU powered on/off in CPU suspend.
- Add mbox driver for tinysys support.

Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
Change-Id: I20141474e1c43cdfacb9f2c6a2285721e50a617c

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fix(mt8188): refine c-state power domain for extensibility

1. MT8188 uses "suspend to RAM" instead of "suspend to idle", so
remove s2idle state.
2. Definition c-state power domain:
- bit[7:4]

fix(mt8188): refine c-state power domain for extensibility

1. MT8188 uses "suspend to RAM" instead of "suspend to idle", so
remove s2idle state.
2. Definition c-state power domain:
- bit[7:4] (main state id):
1: Cluster.
2: Mcusys.
3: Memory.
4: System pll.
5: System bus.
6: SoC 26m/DCXO.
7: Vcore buck.
15: Suspend.
- bit[3:0] (reserved for state_id extension):
4: CPU buck.

Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Change-Id: Ibacd3d642f78726e1f1c08f18892481d2695f9e6

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Merge "refactor(psci): unify psci_is_last_on_cpu and psci_is_last_on_cpu_safe" into integration

feat(stm32mp1): add plat_report_*_abort functions

The new helpers are created in STM32MP1 platform for prefetch and data
aborts.
While at it, put plat_report_exception() under DEBUG flag. If DEBUG i

feat(stm32mp1): add plat_report_*_abort functions

The new helpers are created in STM32MP1 platform for prefetch and data
aborts.
While at it, put plat_report_exception() under DEBUG flag. If DEBUG is
not set, the weak function which does the same will be used.
This plat_report_exception() function can also be simplified, as it will
no more be used to report aborts.

Change-Id: Ibe989b28e236693f317cffb0545ea0611b7bdde4
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(debug): add helpers for aborts on AARCH32

New helper functions are created to handle data & prefetch aborts
in AARCH32. They call platform functions, just like what
report_exception is doing.
A

feat(debug): add helpers for aborts on AARCH32

New helper functions are created to handle data & prefetch aborts
in AARCH32. They call platform functions, just like what
report_exception is doing.
As extended MSR/MRS instructions (to access lr_abt in monitor mode)
are only available if CPU (Armv7) has virtualization extension,
the functions branch to original report_exception handlers if this is
not the case.
Those new helpers are created mainly to distinguish data and prefetch
aborts, as they both share the same mode.
This adds 40 bytes of code.

Change-Id: I5dd31930344ad4e3a658f8a9d366a87a300aeb67
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(debug): add AARCH32 CP15 fault registers

For an easier debug on Aarch32, in case of abort, it is useful to access
DFSR, IFSR, DFAR and IFAR CP15 registers.

Change-Id: Ie6b5a2882cd701f76e9d455e

feat(debug): add AARCH32 CP15 fault registers

For an easier debug on Aarch32, in case of abort, it is useful to access
DFSR, IFSR, DFAR and IFAR CP15 registers.

Change-Id: Ie6b5a2882cd701f76e9d455ec43bd4b0fbe3cc78
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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