1 /* 2 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <common/desc_image_load.h> 15 #include <drivers/generic_delay_timer.h> 16 #include <drivers/mmc.h> 17 #include <drivers/st/bsec.h> 18 #include <drivers/st/regulator_fixed.h> 19 #include <drivers/st/stm32_iwdg.h> 20 #include <drivers/st/stm32_rng.h> 21 #include <drivers/st/stm32_uart.h> 22 #include <drivers/st/stm32mp1_clk.h> 23 #include <drivers/st/stm32mp1_pwr.h> 24 #include <drivers/st/stm32mp1_ram.h> 25 #include <drivers/st/stm32mp_pmic.h> 26 #include <lib/fconf/fconf.h> 27 #include <lib/fconf/fconf_dyn_cfg_getter.h> 28 #include <lib/mmio.h> 29 #include <lib/optee_utils.h> 30 #include <lib/xlat_tables/xlat_tables_v2.h> 31 #include <plat/common/platform.h> 32 33 #include <platform_def.h> 34 #include <stm32mp_common.h> 35 #include <stm32mp1_dbgmcu.h> 36 37 #if DEBUG 38 static const char debug_msg[] = { 39 "***************************************************\n" 40 "** DEBUG ACCESS PORT IS OPEN! **\n" 41 "** This boot image is only for debugging purpose **\n" 42 "** and is unsafe for production use. **\n" 43 "** **\n" 44 "** If you see this message and you are not **\n" 45 "** debugging report this immediately to your **\n" 46 "** vendor! **\n" 47 "***************************************************\n" 48 }; 49 #endif 50 51 #if STM32MP15 52 static struct stm32mp_auth_ops stm32mp1_auth_ops; 53 #endif 54 55 static void print_reset_reason(void) 56 { 57 uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR); 58 59 if (rstsr == 0U) { 60 WARN("Reset reason unknown\n"); 61 return; 62 } 63 64 INFO("Reset reason (0x%x):\n", rstsr); 65 66 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) { 67 if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) { 68 INFO("System exits from STANDBY\n"); 69 return; 70 } 71 72 if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) { 73 INFO("MPU exits from CSTANDBY\n"); 74 return; 75 } 76 } 77 78 if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) { 79 INFO(" Power-on Reset (rst_por)\n"); 80 return; 81 } 82 83 if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) { 84 INFO(" Brownout Reset (rst_bor)\n"); 85 return; 86 } 87 88 #if STM32MP15 89 if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) { 90 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 91 INFO(" System reset generated by MCU (MCSYSRST)\n"); 92 } else { 93 INFO(" Local reset generated by MCU (MCSYSRST)\n"); 94 } 95 return; 96 } 97 #endif 98 99 if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) { 100 INFO(" System reset generated by MPU (MPSYSRST)\n"); 101 return; 102 } 103 104 if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) { 105 INFO(" Reset due to a clock failure on HSE\n"); 106 return; 107 } 108 109 if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) { 110 INFO(" IWDG1 Reset (rst_iwdg1)\n"); 111 return; 112 } 113 114 if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) { 115 INFO(" IWDG2 Reset (rst_iwdg2)\n"); 116 return; 117 } 118 119 if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) { 120 INFO(" MPU Processor 0 Reset\n"); 121 return; 122 } 123 124 #if STM32MP15 125 if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) { 126 INFO(" MPU Processor 1 Reset\n"); 127 return; 128 } 129 #endif 130 131 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 132 INFO(" Pad Reset from NRST\n"); 133 return; 134 } 135 136 if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) { 137 INFO(" Reset due to a failure of VDD_CORE\n"); 138 return; 139 } 140 141 ERROR(" Unidentified reset reason\n"); 142 } 143 144 void bl2_el3_early_platform_setup(u_register_t arg0, 145 u_register_t arg1 __unused, 146 u_register_t arg2 __unused, 147 u_register_t arg3 __unused) 148 { 149 stm32mp_setup_early_console(); 150 151 stm32mp_save_boot_ctx_address(arg0); 152 } 153 154 void bl2_platform_setup(void) 155 { 156 int ret; 157 158 ret = stm32mp1_ddr_probe(); 159 if (ret < 0) { 160 ERROR("Invalid DDR init: error %d\n", ret); 161 panic(); 162 } 163 164 /* Map DDR for binary load, now with cacheable attribute */ 165 ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE, 166 STM32MP_DDR_MAX_SIZE, MT_MEMORY | MT_RW | MT_SECURE); 167 if (ret < 0) { 168 ERROR("DDR mapping: error %d\n", ret); 169 panic(); 170 } 171 172 #if STM32MP_USE_STM32IMAGE 173 #ifdef AARCH32_SP_OPTEE 174 INFO("BL2 runs OP-TEE setup\n"); 175 #else 176 INFO("BL2 runs SP_MIN setup\n"); 177 #endif 178 #endif /* STM32MP_USE_STM32IMAGE */ 179 } 180 181 #if STM32MP15 182 static void update_monotonic_counter(void) 183 { 184 uint32_t version; 185 uint32_t otp; 186 187 CASSERT(STM32_TF_VERSION <= MAX_MONOTONIC_VALUE, 188 assert_stm32mp1_monotonic_counter_reach_max); 189 190 /* Check if monotonic counter needs to be incremented */ 191 if (stm32_get_otp_index(MONOTONIC_OTP, &otp, NULL) != 0) { 192 panic(); 193 } 194 195 if (stm32_get_otp_value_from_idx(otp, &version) != 0) { 196 panic(); 197 } 198 199 if ((version + 1U) < BIT(STM32_TF_VERSION)) { 200 uint32_t result; 201 202 /* Need to increment the monotonic counter. */ 203 version = BIT(STM32_TF_VERSION) - 1U; 204 205 result = bsec_program_otp(version, otp); 206 if (result != BSEC_OK) { 207 ERROR("BSEC: MONOTONIC_OTP program Error %u\n", 208 result); 209 panic(); 210 } 211 INFO("Monotonic counter has been incremented (value 0x%x)\n", 212 version); 213 } 214 } 215 #endif 216 217 void bl2_el3_plat_arch_setup(void) 218 { 219 const char *board_model; 220 boot_api_context_t *boot_context = 221 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 222 uintptr_t pwr_base; 223 uintptr_t rcc_base; 224 225 if (bsec_probe() != 0U) { 226 panic(); 227 } 228 229 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 230 BL_CODE_END - BL_CODE_BASE, 231 MT_CODE | MT_SECURE); 232 233 #if STM32MP_USE_STM32IMAGE 234 #ifdef AARCH32_SP_OPTEE 235 mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE, 236 STM32MP_OPTEE_SIZE, 237 MT_MEMORY | MT_RW | MT_SECURE); 238 #else 239 /* Prevent corruption of preloaded BL32 */ 240 mmap_add_region(BL32_BASE, BL32_BASE, 241 BL32_LIMIT - BL32_BASE, 242 MT_RO_DATA | MT_SECURE); 243 #endif 244 #endif /* STM32MP_USE_STM32IMAGE */ 245 246 /* Prevent corruption of preloaded Device Tree */ 247 mmap_add_region(DTB_BASE, DTB_BASE, 248 DTB_LIMIT - DTB_BASE, 249 MT_RO_DATA | MT_SECURE); 250 251 configure_mmu(); 252 253 if (dt_open_and_check(STM32MP_DTB_BASE) < 0) { 254 panic(); 255 } 256 257 pwr_base = stm32mp_pwr_base(); 258 rcc_base = stm32mp_rcc_base(); 259 260 /* 261 * Disable the backup domain write protection. 262 * The protection is enable at each reset by hardware 263 * and must be disabled by software. 264 */ 265 mmio_setbits_32(pwr_base + PWR_CR1, PWR_CR1_DBP); 266 267 while ((mmio_read_32(pwr_base + PWR_CR1) & PWR_CR1_DBP) == 0U) { 268 ; 269 } 270 271 /* Reset backup domain on cold boot cases */ 272 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) { 273 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 274 275 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == 276 0U) { 277 ; 278 } 279 280 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 281 } 282 283 #if STM32MP15 284 /* Disable MCKPROT */ 285 mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT); 286 #endif 287 288 /* 289 * Set minimum reset pulse duration to 31ms for discrete power 290 * supplied boards. 291 */ 292 if (dt_pmic_status() <= 0) { 293 mmio_clrsetbits_32(rcc_base + RCC_RDLSICR, 294 RCC_RDLSICR_MRD_MASK, 295 31U << RCC_RDLSICR_MRD_SHIFT); 296 } 297 298 generic_delay_timer_init(); 299 300 #if STM32MP_UART_PROGRAMMER 301 /* Disable programmer UART before changing clock tree */ 302 if (boot_context->boot_interface_selected == 303 BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART) { 304 uintptr_t uart_prog_addr = 305 get_uart_address(boot_context->boot_interface_instance); 306 307 stm32_uart_stop(uart_prog_addr); 308 } 309 #endif 310 if (stm32mp1_clk_probe() < 0) { 311 panic(); 312 } 313 314 if (stm32mp1_clk_init() < 0) { 315 panic(); 316 } 317 318 stm32_save_boot_interface(boot_context->boot_interface_selected, 319 boot_context->boot_interface_instance); 320 stm32_save_boot_auth(boot_context->auth_status, 321 boot_context->boot_partition_used_toboot); 322 323 #if STM32MP_USB_PROGRAMMER && STM32MP15 324 /* Deconfigure all UART RX pins configured by ROM code */ 325 stm32mp1_deconfigure_uart_pins(); 326 #endif 327 328 if (stm32mp_uart_console_setup() != 0) { 329 goto skip_console_init; 330 } 331 332 stm32mp_print_cpuinfo(); 333 334 board_model = dt_get_board_model(); 335 if (board_model != NULL) { 336 NOTICE("Model: %s\n", board_model); 337 } 338 339 stm32mp_print_boardinfo(); 340 341 if (boot_context->auth_status != BOOT_API_CTX_AUTH_NO) { 342 NOTICE("Bootrom authentication %s\n", 343 (boot_context->auth_status == BOOT_API_CTX_AUTH_FAILED) ? 344 "failed" : "succeeded"); 345 } 346 347 skip_console_init: 348 if (fixed_regulator_register() != 0) { 349 panic(); 350 } 351 352 if (dt_pmic_status() > 0) { 353 initialize_pmic(); 354 if (pmic_voltages_init() != 0) { 355 ERROR("PMIC voltages init failed\n"); 356 panic(); 357 } 358 print_pmic_info_and_debug(); 359 } 360 361 stm32mp1_syscfg_init(); 362 363 if (stm32_iwdg_init() < 0) { 364 panic(); 365 } 366 367 stm32_iwdg_refresh(); 368 369 if (bsec_read_debug_conf() != 0U) { 370 if (stm32mp_is_closed_device()) { 371 #if DEBUG 372 WARN("\n%s", debug_msg); 373 #else 374 ERROR("***Debug opened on closed chip***\n"); 375 #endif 376 } 377 } 378 379 #if STM32MP13 380 if (stm32_rng_init() != 0) { 381 panic(); 382 } 383 #endif 384 385 #if STM32MP15 386 if (stm32mp_is_auth_supported()) { 387 stm32mp1_auth_ops.check_key = 388 boot_context->bootrom_ecdsa_check_key; 389 stm32mp1_auth_ops.verify_signature = 390 boot_context->bootrom_ecdsa_verify_signature; 391 392 stm32mp_init_auth(&stm32mp1_auth_ops); 393 } 394 #endif 395 396 stm32mp1_arch_security_setup(); 397 398 print_reset_reason(); 399 400 #if STM32MP15 401 update_monotonic_counter(); 402 #endif 403 404 stm32mp1_syscfg_enable_io_compensation_finish(); 405 406 #if !STM32MP_USE_STM32IMAGE 407 fconf_populate("TB_FW", STM32MP_DTB_BASE); 408 #endif /* !STM32MP_USE_STM32IMAGE */ 409 410 stm32mp_io_setup(); 411 } 412 413 /******************************************************************************* 414 * This function can be used by the platforms to update/use image 415 * information for given `image_id`. 416 ******************************************************************************/ 417 int bl2_plat_handle_post_image_load(unsigned int image_id) 418 { 419 int err = 0; 420 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 421 bl_mem_params_node_t *bl32_mem_params; 422 bl_mem_params_node_t *pager_mem_params __unused; 423 bl_mem_params_node_t *paged_mem_params __unused; 424 #if !STM32MP_USE_STM32IMAGE 425 const struct dyn_cfg_dtb_info_t *config_info; 426 bl_mem_params_node_t *tos_fw_mem_params; 427 unsigned int i; 428 unsigned int idx; 429 unsigned long long ddr_top __unused; 430 const unsigned int image_ids[] = { 431 BL32_IMAGE_ID, 432 BL33_IMAGE_ID, 433 HW_CONFIG_ID, 434 TOS_FW_CONFIG_ID, 435 }; 436 #endif /* !STM32MP_USE_STM32IMAGE */ 437 438 assert(bl_mem_params != NULL); 439 440 switch (image_id) { 441 #if !STM32MP_USE_STM32IMAGE 442 case FW_CONFIG_ID: 443 /* Set global DTB info for fixed fw_config information */ 444 set_config_info(STM32MP_FW_CONFIG_BASE, ~0UL, STM32MP_FW_CONFIG_MAX_SIZE, 445 FW_CONFIG_ID); 446 fconf_populate("FW_CONFIG", STM32MP_FW_CONFIG_BASE); 447 448 idx = dyn_cfg_dtb_info_get_index(TOS_FW_CONFIG_ID); 449 450 /* Iterate through all the fw config IDs */ 451 for (i = 0U; i < ARRAY_SIZE(image_ids); i++) { 452 if ((image_ids[i] == TOS_FW_CONFIG_ID) && (idx == FCONF_INVALID_IDX)) { 453 continue; 454 } 455 456 bl_mem_params = get_bl_mem_params_node(image_ids[i]); 457 assert(bl_mem_params != NULL); 458 459 config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, image_ids[i]); 460 if (config_info == NULL) { 461 continue; 462 } 463 464 bl_mem_params->image_info.image_base = config_info->config_addr; 465 bl_mem_params->image_info.image_max_size = config_info->config_max_size; 466 467 bl_mem_params->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING; 468 469 switch (image_ids[i]) { 470 case BL32_IMAGE_ID: 471 bl_mem_params->ep_info.pc = config_info->config_addr; 472 473 /* In case of OPTEE, initialize address space with tos_fw addr */ 474 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 475 assert(pager_mem_params != NULL); 476 pager_mem_params->image_info.image_base = config_info->config_addr; 477 pager_mem_params->image_info.image_max_size = 478 config_info->config_max_size; 479 480 /* Init base and size for pager if exist */ 481 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 482 if (paged_mem_params != NULL) { 483 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + 484 (dt_get_ddr_size() - STM32MP_DDR_S_SIZE - 485 STM32MP_DDR_SHMEM_SIZE); 486 paged_mem_params->image_info.image_max_size = 487 STM32MP_DDR_S_SIZE; 488 } 489 break; 490 491 case BL33_IMAGE_ID: 492 bl_mem_params->ep_info.pc = config_info->config_addr; 493 break; 494 495 case HW_CONFIG_ID: 496 case TOS_FW_CONFIG_ID: 497 break; 498 499 default: 500 return -EINVAL; 501 } 502 } 503 break; 504 #endif /* !STM32MP_USE_STM32IMAGE */ 505 506 case BL32_IMAGE_ID: 507 if (optee_header_is_valid(bl_mem_params->image_info.image_base)) { 508 image_info_t *paged_image_info = NULL; 509 510 /* BL32 is OP-TEE header */ 511 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; 512 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 513 assert(pager_mem_params != NULL); 514 515 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 516 if (paged_mem_params != NULL) { 517 paged_image_info = &paged_mem_params->image_info; 518 } 519 520 #if STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) 521 /* Set OP-TEE extra image load areas at run-time */ 522 pager_mem_params->image_info.image_base = STM32MP_OPTEE_BASE; 523 pager_mem_params->image_info.image_max_size = STM32MP_OPTEE_SIZE; 524 525 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + 526 dt_get_ddr_size() - 527 STM32MP_DDR_S_SIZE - 528 STM32MP_DDR_SHMEM_SIZE; 529 paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE; 530 #endif /* STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) */ 531 532 err = parse_optee_header(&bl_mem_params->ep_info, 533 &pager_mem_params->image_info, 534 paged_image_info); 535 if (err != 0) { 536 ERROR("OPTEE header parse error.\n"); 537 panic(); 538 } 539 540 /* Set optee boot info from parsed header data */ 541 if (paged_mem_params != NULL) { 542 bl_mem_params->ep_info.args.arg0 = 543 paged_mem_params->image_info.image_base; 544 } else { 545 bl_mem_params->ep_info.args.arg0 = 0U; 546 } 547 548 bl_mem_params->ep_info.args.arg1 = 0U; /* Unused */ 549 bl_mem_params->ep_info.args.arg2 = 0U; /* No DT supported */ 550 } else { 551 #if !STM32MP_USE_STM32IMAGE 552 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; 553 tos_fw_mem_params = get_bl_mem_params_node(TOS_FW_CONFIG_ID); 554 assert(tos_fw_mem_params != NULL); 555 bl_mem_params->image_info.image_max_size += 556 tos_fw_mem_params->image_info.image_max_size; 557 #endif /* !STM32MP_USE_STM32IMAGE */ 558 bl_mem_params->ep_info.args.arg0 = 0; 559 } 560 break; 561 562 case BL33_IMAGE_ID: 563 bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID); 564 assert(bl32_mem_params != NULL); 565 bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc; 566 #if !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT 567 stm32mp1_fwu_set_boot_idx(); 568 #endif /* !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT */ 569 break; 570 571 default: 572 /* Do nothing in default case */ 573 break; 574 } 575 576 #if STM32MP_SDMMC || STM32MP_EMMC 577 /* 578 * Invalidate remaining data read from MMC but not flushed by load_image_flush(). 579 * We take the worst case which is 2 MMC blocks. 580 */ 581 if ((image_id != FW_CONFIG_ID) && 582 ((bl_mem_params->image_info.h.attr & IMAGE_ATTRIB_SKIP_LOADING) == 0U)) { 583 inv_dcache_range(bl_mem_params->image_info.image_base + 584 bl_mem_params->image_info.image_size, 585 2U * MMC_BLOCK_SIZE); 586 } 587 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 588 589 return err; 590 } 591 592 void bl2_el3_plat_prepare_exit(void) 593 { 594 uint16_t boot_itf = stm32mp_get_boot_itf_selected(); 595 596 switch (boot_itf) { 597 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER 598 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART: 599 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB: 600 /* Invalidate the downloaded buffer used with io_memmap */ 601 inv_dcache_range(DWL_BUFFER_BASE, DWL_BUFFER_SIZE); 602 break; 603 #endif /* STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER */ 604 default: 605 /* Do nothing in default case */ 606 break; 607 } 608 609 stm32mp1_security_setup(); 610 } 611