refactor(security): add OpenSSL 1.x compatibility

When updated to work with OpenSSL 3.0, the host tools lost their
compatibility with previous versions (1.x) of OpenSSL. This is
mainly due to the fa

refactor(security): add OpenSSL 1.x compatibility

When updated to work with OpenSSL 3.0, the host tools lost their
compatibility with previous versions (1.x) of OpenSSL. This is
mainly due to the fact that 1.x APIs became deprecated in 3.0 and
therefore their use cause compiling errors. In addition, updating
for a newer version of OpenSSL meant improving the stability
against security threats. However, although version 1.1.1 is
now deprecated, it still receives security updates, so it would
not imply major security issues to keep compatibility with it too.

This patch adds backwards compatibility with OpenSSL 1.x versions
by adding back 1.x API code. It defines a macro USING_OPENSSL3,
which will select the appropriate OpenSSL API version depending on
the OpenSSL library path chosen (which is determined by the
already-existing OPENSSL_DIR variable).

In addition, cleanup items were packed in functions and moved to
the proper modules in order to make the code more maintainable and
legible.

Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: I8deceb5e419edc73277792861882404790ccd33c

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Merge "fix(docs): add LTS maintainers" into integration

Merge "feat(cpus): make cache ops conditional" into integration

fix(docs): add LTS maintainers

Adding the maintainers for the TF-A LTS releases.

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I683885b8b52c0d004218fa52f71a245bd26b1229

Merge "fix(pmu): add sensible default for MDCR_EL2" into integration

Merge "build: deprecate Arm TC0 FVP platform" into integration

fix(pmu): add sensible default for MDCR_EL2

When TF-A is set to save and restore EL2 registers it initially zeroes
all of them so that it does not leak any information. However,
MDCR_EL2.HPMN of 0 i

fix(pmu): add sensible default for MDCR_EL2

When TF-A is set to save and restore EL2 registers it initially zeroes
all of them so that it does not leak any information. However,
MDCR_EL2.HPMN of 0 is poorly defined when FEAT_HPMN0 is not implemented.
Set it to its hardware reset value so that lower ELs don't inherit a
wrong value.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I8055005ef9b6eaafefa13b62a0b41289079fdd23

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build: deprecate Arm TC0 FVP platform

Arm has decided to deprecate the TC0 platform. The development of
software and fast models for TC0 platform has been discontinued.
TC0 platform has been superse

build: deprecate Arm TC0 FVP platform

Arm has decided to deprecate the TC0 platform. The development of
software and fast models for TC0 platform has been discontinued.
TC0 platform has been superseded by the TC1 and TC2 platforms,
which are already supported in TF-A and CI repositories.

Change-Id: I0269816a6ee733f732669027eae4e14cd60b6084
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "fix(cpus): workaround for Cortex-A77 erratum 2743100" into integration

Merge "fix(docs): update maintainers list" into integration

fix(docs): update maintainers list

As part of release process revisit list of maintainers to keep
it updated.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I63b87265a6bff00ad05d8

fix(docs): update maintainers list

As part of release process revisit list of maintainers to keep
it updated.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I63b87265a6bff00ad05d8b3b7cad694cdf48e9ea

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Merge "chore(docs): fix broken url references to arm procedure call" into integration

Merge changes from topic "mp/ras_refactoring" into integration

* changes:
docs: document do_panic() and panic() helper functions
fix(ras): restrict RAS support for NS world

chore(docs): fix broken url references to arm procedure call

Couple for urls under section: `5.6. Use of built-in C and libc
data types` from docs has broken urls since the new arm procedure
call do

chore(docs): fix broken url references to arm procedure call

Couple for urls under section: `5.6. Use of built-in C and libc
data types` from docs has broken urls since the new arm procedure
call doc is moved to be part of `ARM-software/abi-aa`.

Change-Id: Ied184ed56c8335d4cbc687e56962439091a18e42
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge changes from topic "mp/ras_refactoring" into integration

* changes:
fix(debug): decouple "get_el_str()" from backtrace
fix(bl31): harden check in delegate_async_ea

fix(cpus): workaround for Cortex-A77 erratum 2743100

Cortex-A77 erratum 2743100 is a Cat B erratum that applies to revisions
r0p0, r1p0, r1p1, and is still open. The workaround is to insert a dsb
be

fix(cpus): workaround for Cortex-A77 erratum 2743100

Cortex-A77 erratum 2743100 is a Cat B erratum that applies to revisions
r0p0, r1p0, r1p1, and is still open. The workaround is to insert a dsb
before the isb in the power down sequence.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1152370/latest

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I8e49a2dac8611f31ace249a17ae7a90cd60e742a

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Merge changes from topic "ffa_el3_spmc_fixes" into integration

* changes:
fix(el3-spmc): check descriptor size for overflow
fix(el3-spmc): fix location of fragment length check
fix(el3-spmc):

Merge changes from topic "ffa_el3_spmc_fixes" into integration

* changes:
fix(el3-spmc): check descriptor size for overflow
fix(el3-spmc): fix location of fragment length check
fix(el3-spmc): fix detection of overlapping memory regions
fix(el3-spmc): fix incomplete reclaim validation

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feat(cpus): make cache ops conditional

When a core is in debug recovery mode its caches are not invalidated
upon reset, so the L1 and L2 cache contents from before reset are
observable after reset.

feat(cpus): make cache ops conditional

When a core is in debug recovery mode its caches are not invalidated
upon reset, so the L1 and L2 cache contents from before reset are
observable after reset. Similarly, debug recovery mode of DynamIQ
cluster ensures that contents of the shared L3 cache are also not
invalidated upon transition to On mode.

Booting cores in debug recovery mode means booting with caches disabled
and preserving the caches until a point where software can dump the
caches and retrieve their contents. TF-A however unconditionally cleans
and invalidates caches at multiple points during boot. This can lead to
memory corruption as well as loss of cache contents to be used for
debugging.

This patch fixes this by calling a platform hook before performing CMOs
in helper routines in cache_helpers.S. The platform hook plat_can_cmo is
an assembly routine which must not clobber x2 and x3, and avoid using
stack. The whole checking is conditional upon `CONDITIONAL_CMO` which
can be set at compile time.

Signed-off-by: Okash Khawaja <okash@google.com>
Change-Id: I172e999e4acd0f872c24056e647cc947ee54b193

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Merge "chore(docs): move deprecated platforms information around" into integration

Merge "build: warn about RSS driver experimental status" into integration

Merge changes from topic "errata" into integration

* changes:
fix(cpus): workaround for Cortex-A76 erratum 2743102
fix(cpus): workaround for Neoverse N1 erratum 2743102

fix(el3-spmc): report execution state in partition info get

Ensure that the correct execution state of an SP is reported
as part of an FF-A v1.1 PARTITION_INFO_GET response.

Signed-off-by: Marc Bon

fix(el3-spmc): report execution state in partition info get

Ensure that the correct execution state of an SP is reported
as part of an FF-A v1.1 PARTITION_INFO_GET response.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I714e53ae71c376463797a42cd5ab7a5e9c687fb7

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Merge "refactor(trng): cleanup the existing TRNG support" into integration

Merge "fix(versal-net): add default values for silicon" into integration

Merge "docs(rme): add instruction to build rmm" into integration