1 /* 2 * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <drivers/clk.h> 10 #include <drivers/st/stm32_gpio.h> 11 #include <drivers/st/stm32_iwdg.h> 12 #include <lib/mmio.h> 13 #include <lib/xlat_tables/xlat_tables_v2.h> 14 #include <libfdt.h> 15 16 #include <plat/common/platform.h> 17 #include <platform_def.h> 18 19 /* Internal layout of the 32bit OTP word board_id */ 20 #define BOARD_ID_BOARD_NB_MASK GENMASK(31, 16) 21 #define BOARD_ID_BOARD_NB_SHIFT 16 22 #define BOARD_ID_VARCPN_MASK GENMASK(15, 12) 23 #define BOARD_ID_VARCPN_SHIFT 12 24 #define BOARD_ID_REVISION_MASK GENMASK(11, 8) 25 #define BOARD_ID_REVISION_SHIFT 8 26 #define BOARD_ID_VARFG_MASK GENMASK(7, 4) 27 #define BOARD_ID_VARFG_SHIFT 4 28 #define BOARD_ID_BOM_MASK GENMASK(3, 0) 29 30 #define BOARD_ID2NB(_id) (((_id) & BOARD_ID_BOARD_NB_MASK) >> \ 31 BOARD_ID_BOARD_NB_SHIFT) 32 #define BOARD_ID2VARCPN(_id) (((_id) & BOARD_ID_VARCPN_MASK) >> \ 33 BOARD_ID_VARCPN_SHIFT) 34 #define BOARD_ID2REV(_id) (((_id) & BOARD_ID_REVISION_MASK) >> \ 35 BOARD_ID_REVISION_SHIFT) 36 #define BOARD_ID2VARFG(_id) (((_id) & BOARD_ID_VARFG_MASK) >> \ 37 BOARD_ID_VARFG_SHIFT) 38 #define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK) 39 40 #if STM32MP13 41 #define TAMP_BOOT_MODE_BACKUP_REG_ID U(30) 42 #endif 43 #if STM32MP15 44 #define TAMP_BOOT_MODE_BACKUP_REG_ID U(20) 45 #endif 46 47 /* 48 * Backup register to store fwu update information. 49 * It should be writeable only by secure world, but also readable by non secure 50 * (so it should be in Zone 2). 51 */ 52 #define TAMP_BOOT_FWU_INFO_REG_ID U(10) 53 #define TAMP_BOOT_FWU_INFO_IDX_MSK GENMASK(3, 0) 54 #define TAMP_BOOT_FWU_INFO_IDX_OFF U(0) 55 #define TAMP_BOOT_FWU_INFO_CNT_MSK GENMASK(7, 4) 56 #define TAMP_BOOT_FWU_INFO_CNT_OFF U(4) 57 58 #if defined(IMAGE_BL2) 59 #define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ 60 STM32MP_SYSRAM_SIZE, \ 61 MT_MEMORY | \ 62 MT_RW | \ 63 MT_SECURE | \ 64 MT_EXECUTE_NEVER) 65 #elif defined(IMAGE_BL32) 66 #define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SEC_SYSRAM_BASE, \ 67 STM32MP_SEC_SYSRAM_SIZE, \ 68 MT_MEMORY | \ 69 MT_RW | \ 70 MT_SECURE | \ 71 MT_EXECUTE_NEVER) 72 73 /* Non-secure SYSRAM is used a uncached memory for SCMI message transfer */ 74 #define MAP_NS_SYSRAM MAP_REGION_FLAT(STM32MP_NS_SYSRAM_BASE, \ 75 STM32MP_NS_SYSRAM_SIZE, \ 76 MT_DEVICE | \ 77 MT_RW | \ 78 MT_NS | \ 79 MT_EXECUTE_NEVER) 80 #endif 81 82 #if STM32MP13 83 #define MAP_SRAM_ALL MAP_REGION_FLAT(SRAMS_BASE, \ 84 SRAMS_SIZE_2MB_ALIGNED, \ 85 MT_MEMORY | \ 86 MT_RW | \ 87 MT_SECURE | \ 88 MT_EXECUTE_NEVER) 89 #endif 90 91 #define MAP_DEVICE1 MAP_REGION_FLAT(STM32MP1_DEVICE1_BASE, \ 92 STM32MP1_DEVICE1_SIZE, \ 93 MT_DEVICE | \ 94 MT_RW | \ 95 MT_SECURE | \ 96 MT_EXECUTE_NEVER) 97 98 #define MAP_DEVICE2 MAP_REGION_FLAT(STM32MP1_DEVICE2_BASE, \ 99 STM32MP1_DEVICE2_SIZE, \ 100 MT_DEVICE | \ 101 MT_RW | \ 102 MT_SECURE | \ 103 MT_EXECUTE_NEVER) 104 105 #if defined(IMAGE_BL2) 106 static const mmap_region_t stm32mp1_mmap[] = { 107 MAP_SEC_SYSRAM, 108 #if STM32MP13 109 MAP_SRAM_ALL, 110 #endif 111 MAP_DEVICE1, 112 #if STM32MP_RAW_NAND 113 MAP_DEVICE2, 114 #endif 115 {0} 116 }; 117 #endif 118 #if defined(IMAGE_BL32) 119 static const mmap_region_t stm32mp1_mmap[] = { 120 MAP_SEC_SYSRAM, 121 MAP_NS_SYSRAM, 122 MAP_DEVICE1, 123 MAP_DEVICE2, 124 {0} 125 }; 126 #endif 127 128 void configure_mmu(void) 129 { 130 mmap_add(stm32mp1_mmap); 131 init_xlat_tables(); 132 133 enable_mmu_svc_mon(0); 134 } 135 136 uintptr_t stm32_get_gpio_bank_base(unsigned int bank) 137 { 138 #if STM32MP13 139 assert((GPIO_BANK_A == 0) && (bank <= GPIO_BANK_I)); 140 #endif 141 #if STM32MP15 142 if (bank == GPIO_BANK_Z) { 143 return GPIOZ_BASE; 144 } 145 146 assert((GPIO_BANK_A == 0) && (bank <= GPIO_BANK_K)); 147 #endif 148 149 return GPIOA_BASE + (bank * GPIO_BANK_OFFSET); 150 } 151 152 uint32_t stm32_get_gpio_bank_offset(unsigned int bank) 153 { 154 #if STM32MP13 155 assert((GPIO_BANK_A == 0) && (bank <= GPIO_BANK_I)); 156 #endif 157 #if STM32MP15 158 if (bank == GPIO_BANK_Z) { 159 return 0; 160 } 161 162 assert((GPIO_BANK_A == 0) && (bank <= GPIO_BANK_K)); 163 #endif 164 165 return bank * GPIO_BANK_OFFSET; 166 } 167 168 bool stm32_gpio_is_secure_at_reset(unsigned int bank) 169 { 170 #if STM32MP13 171 return true; 172 #endif 173 #if STM32MP15 174 if (bank == GPIO_BANK_Z) { 175 return true; 176 } 177 178 return false; 179 #endif 180 } 181 182 unsigned long stm32_get_gpio_bank_clock(unsigned int bank) 183 { 184 #if STM32MP13 185 assert((GPIO_BANK_A == 0) && (bank <= GPIO_BANK_I)); 186 #endif 187 #if STM32MP15 188 if (bank == GPIO_BANK_Z) { 189 return GPIOZ; 190 } 191 192 assert((GPIO_BANK_A == 0) && (bank <= GPIO_BANK_K)); 193 #endif 194 195 return GPIOA + (bank - GPIO_BANK_A); 196 } 197 198 int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank) 199 { 200 const char *node_compatible = NULL; 201 202 switch (bank) { 203 case GPIO_BANK_A: 204 case GPIO_BANK_B: 205 case GPIO_BANK_C: 206 case GPIO_BANK_D: 207 case GPIO_BANK_E: 208 case GPIO_BANK_F: 209 case GPIO_BANK_G: 210 case GPIO_BANK_H: 211 case GPIO_BANK_I: 212 #if STM32MP13 213 node_compatible = "st,stm32mp135-pinctrl"; 214 break; 215 #endif 216 #if STM32MP15 217 case GPIO_BANK_J: 218 case GPIO_BANK_K: 219 node_compatible = "st,stm32mp157-pinctrl"; 220 break; 221 case GPIO_BANK_Z: 222 node_compatible = "st,stm32mp157-z-pinctrl"; 223 break; 224 #endif 225 default: 226 panic(); 227 } 228 229 return fdt_node_offset_by_compatible(fdt, -1, node_compatible); 230 } 231 232 #if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2) 233 /* 234 * UART Management 235 */ 236 static const uintptr_t stm32mp1_uart_addresses[8] = { 237 USART1_BASE, 238 USART2_BASE, 239 USART3_BASE, 240 UART4_BASE, 241 UART5_BASE, 242 USART6_BASE, 243 UART7_BASE, 244 UART8_BASE, 245 }; 246 247 uintptr_t get_uart_address(uint32_t instance_nb) 248 { 249 if ((instance_nb == 0U) || 250 (instance_nb > ARRAY_SIZE(stm32mp1_uart_addresses))) { 251 return 0U; 252 } 253 254 return stm32mp1_uart_addresses[instance_nb - 1U]; 255 } 256 #endif 257 258 #if STM32MP_USB_PROGRAMMER 259 struct gpio_bank_pin_list { 260 uint32_t bank; 261 uint32_t pin; 262 }; 263 264 static const struct gpio_bank_pin_list gpio_list[] = { 265 { /* USART2_RX: GPIOA3 */ 266 .bank = 0U, 267 .pin = 3U, 268 }, 269 { /* USART3_RX: GPIOB12 */ 270 .bank = 1U, 271 .pin = 12U, 272 }, 273 { /* UART4_RX: GPIOB2 */ 274 .bank = 1U, 275 .pin = 2U, 276 }, 277 { /* UART5_RX: GPIOB4 */ 278 .bank = 1U, 279 .pin = 5U, 280 }, 281 { /* USART6_RX: GPIOC7 */ 282 .bank = 2U, 283 .pin = 7U, 284 }, 285 { /* UART7_RX: GPIOF6 */ 286 .bank = 5U, 287 .pin = 6U, 288 }, 289 { /* UART8_RX: GPIOE0 */ 290 .bank = 4U, 291 .pin = 0U, 292 }, 293 }; 294 295 void stm32mp1_deconfigure_uart_pins(void) 296 { 297 size_t i; 298 299 for (i = 0U; i < ARRAY_SIZE(gpio_list); i++) { 300 set_gpio_reset_cfg(gpio_list[i].bank, gpio_list[i].pin); 301 } 302 } 303 #endif 304 305 uint32_t stm32mp_get_chip_version(void) 306 { 307 #if STM32MP13 308 return stm32mp1_syscfg_get_chip_version(); 309 #endif 310 #if STM32MP15 311 uint32_t version = 0U; 312 313 if (stm32mp1_dbgmcu_get_chip_version(&version) < 0) { 314 INFO("Cannot get CPU version, debug disabled\n"); 315 return 0U; 316 } 317 318 return version; 319 #endif 320 } 321 322 uint32_t stm32mp_get_chip_dev_id(void) 323 { 324 #if STM32MP13 325 return stm32mp1_syscfg_get_chip_dev_id(); 326 #endif 327 #if STM32MP15 328 uint32_t dev_id; 329 330 if (stm32mp1_dbgmcu_get_chip_dev_id(&dev_id) < 0) { 331 INFO("Use default chip ID, debug disabled\n"); 332 dev_id = STM32MP1_CHIP_ID; 333 } 334 335 return dev_id; 336 #endif 337 } 338 339 static uint32_t get_part_number(void) 340 { 341 static uint32_t part_number; 342 343 if (part_number != 0U) { 344 return part_number; 345 } 346 347 if (stm32_get_otp_value(PART_NUMBER_OTP, &part_number) != 0) { 348 panic(); 349 } 350 351 part_number = (part_number & PART_NUMBER_OTP_PART_MASK) >> 352 PART_NUMBER_OTP_PART_SHIFT; 353 354 part_number |= stm32mp_get_chip_dev_id() << 16; 355 356 return part_number; 357 } 358 359 #if STM32MP15 360 static uint32_t get_cpu_package(void) 361 { 362 uint32_t package; 363 364 if (stm32_get_otp_value(PACKAGE_OTP, &package) != 0) { 365 panic(); 366 } 367 368 package = (package & PACKAGE_OTP_PKG_MASK) >> 369 PACKAGE_OTP_PKG_SHIFT; 370 371 return package; 372 } 373 #endif 374 375 void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]) 376 { 377 const char *cpu_s, *cpu_r, *pkg; 378 379 /* MPUs Part Numbers */ 380 switch (get_part_number()) { 381 #if STM32MP13 382 case STM32MP135F_PART_NB: 383 cpu_s = "135F"; 384 break; 385 case STM32MP135D_PART_NB: 386 cpu_s = "135D"; 387 break; 388 case STM32MP135C_PART_NB: 389 cpu_s = "135C"; 390 break; 391 case STM32MP135A_PART_NB: 392 cpu_s = "135A"; 393 break; 394 case STM32MP133F_PART_NB: 395 cpu_s = "133F"; 396 break; 397 case STM32MP133D_PART_NB: 398 cpu_s = "133D"; 399 break; 400 case STM32MP133C_PART_NB: 401 cpu_s = "133C"; 402 break; 403 case STM32MP133A_PART_NB: 404 cpu_s = "133A"; 405 break; 406 case STM32MP131F_PART_NB: 407 cpu_s = "131F"; 408 break; 409 case STM32MP131D_PART_NB: 410 cpu_s = "131D"; 411 break; 412 case STM32MP131C_PART_NB: 413 cpu_s = "131C"; 414 break; 415 case STM32MP131A_PART_NB: 416 cpu_s = "131A"; 417 break; 418 #endif 419 #if STM32MP15 420 case STM32MP157C_PART_NB: 421 cpu_s = "157C"; 422 break; 423 case STM32MP157A_PART_NB: 424 cpu_s = "157A"; 425 break; 426 case STM32MP153C_PART_NB: 427 cpu_s = "153C"; 428 break; 429 case STM32MP153A_PART_NB: 430 cpu_s = "153A"; 431 break; 432 case STM32MP151C_PART_NB: 433 cpu_s = "151C"; 434 break; 435 case STM32MP151A_PART_NB: 436 cpu_s = "151A"; 437 break; 438 case STM32MP157F_PART_NB: 439 cpu_s = "157F"; 440 break; 441 case STM32MP157D_PART_NB: 442 cpu_s = "157D"; 443 break; 444 case STM32MP153F_PART_NB: 445 cpu_s = "153F"; 446 break; 447 case STM32MP153D_PART_NB: 448 cpu_s = "153D"; 449 break; 450 case STM32MP151F_PART_NB: 451 cpu_s = "151F"; 452 break; 453 case STM32MP151D_PART_NB: 454 cpu_s = "151D"; 455 break; 456 #endif 457 default: 458 cpu_s = "????"; 459 break; 460 } 461 462 /* Package */ 463 #if STM32MP13 464 /* On STM32MP13, package is not present in OTP */ 465 pkg = ""; 466 #endif 467 #if STM32MP15 468 switch (get_cpu_package()) { 469 case PKG_AA_LFBGA448: 470 pkg = "AA"; 471 break; 472 case PKG_AB_LFBGA354: 473 pkg = "AB"; 474 break; 475 case PKG_AC_TFBGA361: 476 pkg = "AC"; 477 break; 478 case PKG_AD_TFBGA257: 479 pkg = "AD"; 480 break; 481 default: 482 pkg = "??"; 483 break; 484 } 485 #endif 486 487 /* REVISION */ 488 switch (stm32mp_get_chip_version()) { 489 case STM32MP1_REV_B: 490 cpu_r = "B"; 491 break; 492 #if STM32MP13 493 case STM32MP1_REV_Y: 494 cpu_r = "Y"; 495 break; 496 #endif 497 case STM32MP1_REV_Z: 498 cpu_r = "Z"; 499 break; 500 default: 501 cpu_r = "?"; 502 break; 503 } 504 505 snprintf(name, STM32_SOC_NAME_SIZE, 506 "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r); 507 } 508 509 void stm32mp_print_cpuinfo(void) 510 { 511 char name[STM32_SOC_NAME_SIZE]; 512 513 stm32mp_get_soc_name(name); 514 NOTICE("CPU: %s\n", name); 515 } 516 517 void stm32mp_print_boardinfo(void) 518 { 519 uint32_t board_id = 0; 520 521 if (stm32_get_otp_value(BOARD_ID_OTP, &board_id) != 0) { 522 return; 523 } 524 525 if (board_id != 0U) { 526 char rev[2]; 527 528 rev[0] = BOARD_ID2REV(board_id) - 1 + 'A'; 529 rev[1] = '\0'; 530 NOTICE("Board: MB%04x Var%u.%u Rev.%s-%02u\n", 531 BOARD_ID2NB(board_id), 532 BOARD_ID2VARCPN(board_id), 533 BOARD_ID2VARFG(board_id), 534 rev, 535 BOARD_ID2BOM(board_id)); 536 } 537 } 538 539 /* Return true when SoC provides a single Cortex-A7 core, and false otherwise */ 540 bool stm32mp_is_single_core(void) 541 { 542 #if STM32MP13 543 return true; 544 #endif 545 #if STM32MP15 546 bool single_core = false; 547 548 switch (get_part_number()) { 549 case STM32MP151A_PART_NB: 550 case STM32MP151C_PART_NB: 551 case STM32MP151D_PART_NB: 552 case STM32MP151F_PART_NB: 553 single_core = true; 554 break; 555 default: 556 break; 557 } 558 559 return single_core; 560 #endif 561 } 562 563 /* Return true when device is in closed state */ 564 bool stm32mp_is_closed_device(void) 565 { 566 uint32_t value; 567 568 if (stm32_get_otp_value(CFG0_OTP, &value) != 0) { 569 return true; 570 } 571 572 #if STM32MP13 573 value = (value & CFG0_OTP_MODE_MASK) >> CFG0_OTP_MODE_SHIFT; 574 575 switch (value) { 576 case CFG0_OPEN_DEVICE: 577 return false; 578 case CFG0_CLOSED_DEVICE: 579 case CFG0_CLOSED_DEVICE_NO_BOUNDARY_SCAN: 580 case CFG0_CLOSED_DEVICE_NO_JTAG: 581 return true; 582 default: 583 panic(); 584 } 585 #endif 586 #if STM32MP15 587 return (value & CFG0_CLOSED_DEVICE) == CFG0_CLOSED_DEVICE; 588 #endif 589 } 590 591 /* Return true when device supports secure boot */ 592 bool stm32mp_is_auth_supported(void) 593 { 594 bool supported = false; 595 596 switch (get_part_number()) { 597 #if STM32MP13 598 case STM32MP131C_PART_NB: 599 case STM32MP131F_PART_NB: 600 case STM32MP133C_PART_NB: 601 case STM32MP133F_PART_NB: 602 case STM32MP135C_PART_NB: 603 case STM32MP135F_PART_NB: 604 #endif 605 #if STM32MP15 606 case STM32MP151C_PART_NB: 607 case STM32MP151F_PART_NB: 608 case STM32MP153C_PART_NB: 609 case STM32MP153F_PART_NB: 610 case STM32MP157C_PART_NB: 611 case STM32MP157F_PART_NB: 612 #endif 613 supported = true; 614 break; 615 default: 616 break; 617 } 618 619 return supported; 620 } 621 622 uint32_t stm32_iwdg_get_instance(uintptr_t base) 623 { 624 switch (base) { 625 case IWDG1_BASE: 626 return IWDG1_INST; 627 case IWDG2_BASE: 628 return IWDG2_INST; 629 default: 630 panic(); 631 } 632 } 633 634 uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst) 635 { 636 uint32_t iwdg_cfg = 0U; 637 uint32_t otp_value; 638 639 if (stm32_get_otp_value(HW2_OTP, &otp_value) != 0) { 640 panic(); 641 } 642 643 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_HW_POS)) != 0U) { 644 iwdg_cfg |= IWDG_HW_ENABLED; 645 } 646 647 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS)) != 0U) { 648 iwdg_cfg |= IWDG_DISABLE_ON_STOP; 649 } 650 651 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS)) != 0U) { 652 iwdg_cfg |= IWDG_DISABLE_ON_STANDBY; 653 } 654 655 return iwdg_cfg; 656 } 657 658 #if defined(IMAGE_BL2) 659 uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags) 660 { 661 uint32_t otp_value; 662 uint32_t otp; 663 uint32_t result; 664 665 if (stm32_get_otp_index(HW2_OTP, &otp, NULL) != 0) { 666 panic(); 667 } 668 669 if (stm32_get_otp_value(HW2_OTP, &otp_value) != 0) { 670 panic(); 671 } 672 673 if ((flags & IWDG_DISABLE_ON_STOP) != 0) { 674 otp_value |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS); 675 } 676 677 if ((flags & IWDG_DISABLE_ON_STANDBY) != 0) { 678 otp_value |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS); 679 } 680 681 result = bsec_write_otp(otp_value, otp); 682 if (result != BSEC_OK) { 683 return result; 684 } 685 686 /* Sticky lock OTP_IWDG (read and write) */ 687 if ((bsec_set_sr_lock(otp) != BSEC_OK) || 688 (bsec_set_sw_lock(otp) != BSEC_OK)) { 689 return BSEC_LOCK_FAIL; 690 } 691 692 return BSEC_OK; 693 } 694 #endif 695 696 uintptr_t stm32_get_bkpr_boot_mode_addr(void) 697 { 698 return tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID); 699 } 700 701 #if PSA_FWU_SUPPORT 702 void stm32mp1_fwu_set_boot_idx(void) 703 { 704 clk_enable(RTCAPB); 705 mmio_clrsetbits_32(tamp_bkpr(TAMP_BOOT_FWU_INFO_REG_ID), 706 TAMP_BOOT_FWU_INFO_IDX_MSK, 707 (plat_fwu_get_boot_idx() << TAMP_BOOT_FWU_INFO_IDX_OFF) & 708 TAMP_BOOT_FWU_INFO_IDX_MSK); 709 clk_disable(RTCAPB); 710 } 711 712 uint32_t stm32_get_and_dec_fwu_trial_boot_cnt(void) 713 { 714 uintptr_t bkpr_fwu_cnt = tamp_bkpr(TAMP_BOOT_FWU_INFO_REG_ID); 715 uint32_t try_cnt; 716 717 clk_enable(RTCAPB); 718 try_cnt = (mmio_read_32(bkpr_fwu_cnt) & TAMP_BOOT_FWU_INFO_CNT_MSK) >> 719 TAMP_BOOT_FWU_INFO_CNT_OFF; 720 721 assert(try_cnt <= FWU_MAX_TRIAL_REBOOT); 722 723 if (try_cnt != 0U) { 724 mmio_clrsetbits_32(bkpr_fwu_cnt, TAMP_BOOT_FWU_INFO_CNT_MSK, 725 (try_cnt - 1U) << TAMP_BOOT_FWU_INFO_CNT_OFF); 726 } 727 clk_disable(RTCAPB); 728 729 return try_cnt; 730 } 731 732 void stm32_set_max_fwu_trial_boot_cnt(void) 733 { 734 uintptr_t bkpr_fwu_cnt = tamp_bkpr(TAMP_BOOT_FWU_INFO_REG_ID); 735 736 clk_enable(RTCAPB); 737 mmio_clrsetbits_32(bkpr_fwu_cnt, TAMP_BOOT_FWU_INFO_CNT_MSK, 738 (FWU_MAX_TRIAL_REBOOT << TAMP_BOOT_FWU_INFO_CNT_OFF) & 739 TAMP_BOOT_FWU_INFO_CNT_MSK); 740 clk_disable(RTCAPB); 741 } 742 #endif /* PSA_FWU_SUPPORT */ 743