Merge "refactor(el3_runtime): remove unnecessary assembly macros" into integration

Merge "fix(mpam): remove unwanted param for "endfunc" macro" into integration

fix(ti): fix typo in boot authentication message name

Fix AUTH_BOOT message identifier (s/IMIAGE/IMAGE).

Reported-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Signed-off-by: Andrew Davis <afd@ti.co

fix(ti): fix typo in boot authentication message name

Fix AUTH_BOOT message identifier (s/IMIAGE/IMAGE).

Reported-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I19eb1798c6b9dd8c3f59e05c59318c9c3be971a0

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refactor(ti): remove empty validate_ns_entrypoint function

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I93165e9f26f5a5b600e7b6a9d48df75d62e89f17

refactor(ti): use console_set_scope() rather than empty function hack

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I62c1215bc02e95a7ea9fa1e2dfa9ef05e204fce1

refactor(ti): factor out common board code into common files

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Ibf7328418c5285a64608b80e7c430a8dee64fb1d

feat(ti): add PSCI system_off support

Send a TI-SCI control message to system firmware to power down the board.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I6b8fa64baa94da078db82fc8e115630c

feat(ti): add PSCI system_off support

Send a TI-SCI control message to system firmware to power down the board.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I6b8fa64baa94da078db82fc8e115630c9f200b3d

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feat(ti): do not handle EAs in EL3

This could be useful if we had extra information to print or
when RAS extensions are available, neither apply here so lets
not trap these in EL3 for now.

Signed-o

feat(ti): do not handle EAs in EL3

This could be useful if we had extra information to print or
when RAS extensions are available, neither apply here so lets
not trap these in EL3 for now.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Ia0334eb845686964e794afe45c7777ea64fd6b0b

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feat(ti): set snoop-delayed exclusive handling on A72 cores

Snoop requests should not be responded to during atomic operations. This
can be handled by the interconnect using its global monitor or by

feat(ti): set snoop-delayed exclusive handling on A72 cores

Snoop requests should not be responded to during atomic operations. This
can be handled by the interconnect using its global monitor or by the
core's SCU delaying to check for the corresponding atomic monitor state.

TI SoCs take the second approach. Set the snoop-delayed exclusive handling
bit to inform the core it needs to delay responses to perform this check.

As J784s4 is currently the only SoC with multiple A72 clusters, limit
this delay to only that device.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I875f64e4f53d47a9a0ccbf3415edc565be7f84d9

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feat(ti): disable L2 dataless UniqueClean evictions

Do this early before we enable caching as a workaround for ARM A72
Errata #854172.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Ic878fdb49

feat(ti): disable L2 dataless UniqueClean evictions

Do this early before we enable caching as a workaround for ARM A72
Errata #854172.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Ic878fdb49e598da0ea6ade012712f8f57023678e

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feat(ti): set L2 cache ECC and and parity on A72 cores

The Cortex-A72 based cores on K3 platforms have cache ECC and
parity protection, enable these.

Signed-off-by: Andrew Davis <afd@ti.com>
Change

feat(ti): set L2 cache ECC and and parity on A72 cores

The Cortex-A72 based cores on K3 platforms have cache ECC and
parity protection, enable these.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Icd00bc4aa9c1c48f0fb2a10ea66e75e0b146ef3c

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feat(ti): set L2 cache data ram latency on A72 cores to 4 cycles

The Cortex-A72 based cores on K3 platforms can be clocked fast
enough that an extra latency cycle is needed to ensure correct
L2 acce

feat(ti): set L2 cache data ram latency on A72 cores to 4 cycles

The Cortex-A72 based cores on K3 platforms can be clocked fast
enough that an extra latency cycle is needed to ensure correct
L2 access. Set the latency here for all A72 cores.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I639091dd0d2de09572bf0f73ac404e306e336883

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Merge changes from topic "tonnad01/rdn2cfg3" into integration

* changes:
feat(rdn2): add platform id value for rdn2 variant 3
refactor(rdn2): reduce use of CSS_SGI_PLATFORM_VARIANT build flag

Merge changes Id4570f91,Ibdf1af70 into integration

* changes:
fix(auth): properly validate X.509 extensions
fix(auth): avoid out-of-bounds read in auth_nvctr()

feat(rdn2): add platform id value for rdn2 variant 3

The RD-N2-Cfg3 platform is a variant of the RD-N2 platform with the
significant difference being the number of ITS blocks and the use of a
differ

feat(rdn2): add platform id value for rdn2 variant 3

The RD-N2-Cfg3 platform is a variant of the RD-N2 platform with the
significant difference being the number of ITS blocks and the use of a
different part number.

Signed-off-by: Tony K Nadackal <tony.nadackal@arm.com>
Change-Id: Id4c5faeae44f21da79cb59540558192d0b02b124

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refactor(rdn2): reduce use of CSS_SGI_PLATFORM_VARIANT build flag

The core count is one of the significant difference between the various
RD-N2 platform variants. The PLAT_ARM_CLUSTER_COUNT macro de

refactor(rdn2): reduce use of CSS_SGI_PLATFORM_VARIANT build flag

The core count is one of the significant difference between the various
RD-N2 platform variants. The PLAT_ARM_CLUSTER_COUNT macro defines the
number of core/cluster for a variant. In preparation to add another
variant of RD-N2 platform, replace the use of CSS_SGI_PLATFORM_VARIANT
build flag, where applicable, with the PLAT_ARM_CLUSTER_COUNT macro.
This helps to reduce the changes required to add support for a new
variant.

Signed-off-by: Tony K Nadackal <tony.nadackal@arm.com>
Change-Id: I89b168308d1b5f7edd402205dd25d6c3a355e100

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Merge changes from topic "fix-power-up-dwn-issue" into integration

* changes:
fix(versal-net): enable wake interrupt during client suspend
fix(versal-net): disable wakeup interrupt during client

Merge changes from topic "fix-power-up-dwn-issue" into integration

* changes:
fix(versal-net): enable wake interrupt during client suspend
fix(versal-net): disable wakeup interrupt during client wakeup
fix(versal-net): clear power down bit during wakeup
fix(versal-net): fix setting power down state
fix(versal-net): clear power down interrupt status before enable
fix(versal-net): resolve misra rule 20.7 warnings
fix(versal-net): resolve misra 10.6 warnings

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Merge "fix(versal): print proper atf handoff source" into integration

Merge "fix(cpus): workaround for Cortex-X2 erratum 2282622" into integration

Merge "fix(cpus): workaround for Cortex-A710 erratum 2282622" into integration

fix(cpus): workaround for Cortex-X2 erratum 2282622

Cortex-X2 erratum 2282622 is a Cat B erratum that applies to
all revisions <=r2p1 and is still open. The workaround is to set
CPUACTLR2_EL1[0] to

fix(cpus): workaround for Cortex-X2 erratum 2282622

Cortex-X2 erratum 2282622 is a Cat B erratum that applies to
all revisions <=r2p1 and is still open. The workaround is to set
CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to behave like
PLD/PRFM LD and not cause invalidations to other PE caches.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1775100/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I43956aa4898a8608eedc5d0dd1471172c641a0c6

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feat(fvp): enable FEAT_HCX by default

FEAT_HCX is one of the features for which Linux necessarily requires EL3
enablement, when the feature is present on a PE.

To cover the effect of different FVP

feat(fvp): enable FEAT_HCX by default

FEAT_HCX is one of the features for which Linux necessarily requires EL3
enablement, when the feature is present on a PE.

To cover the effect of different FVP command line parameters, include
the feature into the standard FVP build, but use FEAT_STATE_CHECK, to
always do runtime checks before accessing feature specific registers.

This prevents a Linux crash when the FVP is called with FEAT_HCX
enabled.

Change-Id: I01aaed15c5a6850176d092b2f0157744fe0a9e13
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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refactor(context-mgmt): move FEAT_HCX save/restore into C

At the moment we save and restore the HCRX_EL2 register in assembly, and
just depend on the build time flags.
To allow runtime checking, and

refactor(context-mgmt): move FEAT_HCX save/restore into C

At the moment we save and restore the HCRX_EL2 register in assembly, and
just depend on the build time flags.
To allow runtime checking, and to avoid too much code in assembly, move
that over to C, and use the new combined build/runtime feature check.

This also allows to drop the assert, since this should now be covered by
the different FEAT_STATE_x options.

Change-Id: I3e20b9ba17121d423cd08edc20bbf4e7ae7c0178
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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refactor(cpufeat): convert FEAT_HCX to new scheme

Use the generic check function in feat_detect.c, and split the feature
check into two functions, as done for FEAT_FGT before.

Signed-off-by: Andre

refactor(cpufeat): convert FEAT_HCX to new scheme

Use the generic check function in feat_detect.c, and split the feature
check into two functions, as done for FEAT_FGT before.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I0a4f973427c10d5d15c414ff5e12b18b7e645fae

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feat(fvp): enable FEAT_FGT by default

FEAT_FGT is one of the features for which Linux necessarily requires EL3
enablement, when the feature is present on a PE.

To cover the effect of different FVP

feat(fvp): enable FEAT_FGT by default

FEAT_FGT is one of the features for which Linux necessarily requires EL3
enablement, when the feature is present on a PE.

To cover the effect of different FVP command line parameters, include
the feature into the standard FVP build, but use FEAT_STATE_CHECK, to
always do runtime checks before accessing feature specific registers.

This prevents a Linux crash when the FVP is called with FEAT_FGT
enabled.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I55fbb2706aefbc3ab67c476e3f8b6ea74ae0d66c

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