Merge changes from topic "sb/doc-updates" into integration

* changes:
docs(porting): remove reference to xlat_table lib v1
docs(porting): remove pull request terminology
docs(changelog): add '

Merge changes from topic "sb/doc-updates" into integration

* changes:
docs(porting): remove reference to xlat_table lib v1
docs(porting): remove pull request terminology
docs(changelog): add 'porting' scope

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docs(porting): remove reference to xlat_table lib v1

Version 1 of the translation table library is deprecated. Refer to
version 2 instead.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.co

docs(porting): remove reference to xlat_table lib v1

Version 1 of the translation table library is deprecated. Refer to
version 2 instead.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I10a4ab7b346ea963345f82baff2deda267c5308d

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docs(porting): remove pull request terminology

The pull request terminology dates back from when TF-A repository was
hosted on Github. Use a terminology that is more suited to Gerrit
workflow.

Sign

docs(porting): remove pull request terminology

The pull request terminology dates back from when TF-A repository was
hosted on Github. Use a terminology that is more suited to Gerrit
workflow.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: Ieecf47617ca1cdb76b9c4a83f63ba3c402b9e975

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docs(changelog): add 'porting' scope

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I22a81b3f69d90e0fcb88c7e98178e915253afb43

Merge "fix(intel): update boot scratch to indicate to Uboot is PSCI ON" into integration

Merge "feat(zynqmp): add hooks for custom runtime setup" into integration

Merge changes Ifd5a63a3,Idb8bda44 into integration

* changes:
fix(intel): flash dcache before mmio read
fix(intel): fix the pointer of block memory to fill in and bytes being set

fix(intel): flash dcache before mmio read

Flash dcache before mmio read to avoid reading old/previous value.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ifd5a63a3c0f20b3e673be62

fix(intel): flash dcache before mmio read

Flash dcache before mmio read to avoid reading old/previous value.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ifd5a63a3c0f20b3e673be62ff5c3b6c4cf69df51

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fix(intel): fix the pointer of block memory to fill in and bytes being set

Fix on the pointer of the block memory to fill in and the number of
bytes to be set. So it can clear the exact address with

fix(intel): fix the pointer of block memory to fill in and bytes being set

Fix on the pointer of the block memory to fill in and the number of
bytes to be set. So it can clear the exact address with exact number
of bytes.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Idb8bda446ecd4c1d85d1ec9802bdcb020904c6c1

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feat(intel): fix bridge disable and reset

Fix bridge sideband manager register clear and set incorrect
implementation. To support non-graceful full bridge disable
and enable.

Signed-off-by: Ang Tie

feat(intel): fix bridge disable and reset

Fix bridge sideband manager register clear and set incorrect
implementation. To support non-graceful full bridge disable
and enable.

Signed-off-by: Ang Tien Sung <tien.sung.ang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I651f3ec163d954e8efb0542ec33bce96e51992db

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fix(intel): update boot scratch to indicate to Uboot is PSCI ON

There is a use case where kernel requested ATF to power off/on only CPU0.
However, after ATF power off/on CPU0, CPU0 did not back into

fix(intel): update boot scratch to indicate to Uboot is PSCI ON

There is a use case where kernel requested ATF to power off/on only CPU0.
However, after ATF power off/on CPU0, CPU0 did not back into the state
to wait for ATF. Instead, CPU0 continue to reentry SPL boot sequence
because CPU0 is master/primary core. This causing the system reboot from
SPL again, while the slave core still in kernel.

To resolve this, ATF is set the boot scratch register 8 bit 17 whenever
it is a request from kernel to power off/on only CPU0. So, if this boot
scratch bit is set, CPU 0 will be able to put into a state to wait for
ATF.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ia0228c5396beaa479858f5bd02fc05139efd2423

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Merge "style(docs): fix typo s/flase/false/" into integration

Merge "fix(scmi): fix compilation error in scmi base" into integration

Merge "docs(threat-model): refresh top-level page" into integration

Merge "fix(fvp): work around DRTM_SUPPORT BL31 progbits exceeded" into integration

feat(zynqmp): add hooks for custom runtime setup

Add runtime setup hooks (via custom_runtime_setup()) for low level
operations related to setting up the system to correct state.

Change-Id: I4af7050

feat(zynqmp): add hooks for custom runtime setup

Add runtime setup hooks (via custom_runtime_setup()) for low level
operations related to setting up the system to correct state.

Change-Id: I4af7050dba2ee2446366d482bef5f5c5dde4bddf
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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Merge changes from topic "cpus" into integration

* changes:
feat(cpus): add support for blackhawk cpu
feat(cpus): add support for chaberton cpu

feat(mt8188): add apu power on/off control

Add mt8188 apu power on/off control

Change-Id: I8e28bf7a4ad4067553981c67c4c2225fdd802859
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>
Signed-of

feat(mt8188): add apu power on/off control

Add mt8188 apu power on/off control

Change-Id: I8e28bf7a4ad4067553981c67c4c2225fdd802859
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>
Signed-off-by: jason-ch chen <Jason-ch.Chen@mediatek.com>

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fix(stm32mp15-fdts): use /omit-if-no-ref/ for spi and i2c

Use /omit-if-no-ref/ keyword in DT to remove extra device nodes only
when they are not used / not referenced.

If the board device tree only

fix(stm32mp15-fdts): use /omit-if-no-ref/ for spi and i2c

Use /omit-if-no-ref/ keyword in DT to remove extra device nodes only
when they are not used / not referenced.

If the board device tree only defines subnodes, dtc does not consider it
as usage, you have to specifically mention device's phandle, e.g.:

\ {
i2c6-phandle = <&i2c6>;
};

or in aliases section
aliases {
i2c6 = &i2c6;
};

Signed-off-by: Vyacheslav Yurkov <uvv.mail@gmail.com>
Change-Id: I431ecd93576f97fd021d82d23b93c659fc8f26b8

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Merge "chore: add dependency files generated by tools to .gitignore" into integration

feat(qemu): increase max cpus per cluster to 16

Qemu-tcg with GICv3 emulation enabled will by default configure MPIDR
topology to report up to 16 cpus per cluster. This is NOT overriden by
qemu's -s

feat(qemu): increase max cpus per cluster to 16

Qemu-tcg with GICv3 emulation enabled will by default configure MPIDR
topology to report up to 16 cpus per cluster. This is NOT overriden by
qemu's -smp setting, e.g. -smp 8,clusters=2,cores=4,threads=1 will still
generate MPIDR reads as if all 8 CPUs were within one cluster.

Increase the hardcoded limit to reflect that so that we accept PSCI
calls that provide MPIDRs based on what was actually read from the
emulated CPU.

Change-Id: Ia321d555f885c96a9a94ae053b340e3a9e300e6d
Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>

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chore: add dependency files generated by tools to .gitignore

In order to avoid git tracking dependency files generated while
compiling tools, the .gitignore list was updated with these files.

Chang

chore: add dependency files generated by tools to .gitignore

In order to avoid git tracking dependency files generated while
compiling tools, the .gitignore list was updated with these files.

Change-Id: I97f1ace40441353779f4f82051d66c478571df38
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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fix(imx8mq): fix compilation with gcc >= 12.x

Starting with GCC >= 12.x the -Wall option includes -Werror=array-bounds
checks. Per default GCC treats all memory accesses below 4096 as NULL,
so acces

fix(imx8mq): fix compilation with gcc >= 12.x

Starting with GCC >= 12.x the -Wall option includes -Werror=array-bounds
checks. Per default GCC treats all memory accesses below 4096 as NULL,
so access to ROMAPI causes the following warning:

------------
In file included from plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c:20:
In function 'mmio_read_8',
inlined from 'imx8mq_soc_info_init' at plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c:70:16,
inlined from 'bl31_platform_setup' at plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c:206:2:
include/lib/mmio.h:19:16: error: array subscript 0 is outside array bounds of 'volatile uint8_t[0]' {aka 'volatile unsigned char[]'} [-Werror=array-bounds]
19 | return *(volatile uint8_t*)addr;
| ^~~~~~~~~~~~~~~~~~~~~~~~
In function 'mmio_read_8',
inlined from 'imx8mq_soc_info_init' at plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c:74:16,
inlined from 'bl31_platform_setup' at plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c:206:2:
include/lib/mmio.h:19:16: error: array subscript 0 is outside array bounds of 'volatile uint8_t[0]' {aka 'volatile unsigned char[]'} [-Werror=array-bounds]
19 | return *(volatile uint8_t*)addr;
| ^~~~~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
------------

This comes arguably from us somewhat abusing pointers to access MMIO
memory regions, which is not really covered by the C language.

Replace the pointer-dereferencing mmio_read_8() with an implementation
that uses inline assembly, to directly generate an 8-bit load
instruction. This avoids the compiler thinking that this access is using
a pointer it needs to jealously look after.

Change-Id: Iab39f6f615d51d3e8a1c54a1262d1e6ec208811d
Reported-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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docs(maintainers): update maintainers for n1sdp/morello

Signed-off-by: Anurag Koul <anurag.koul@arm.com>
Change-Id: I305d03ae664f7d6124bf73d3bfdd81d34d760065

feat(cpus): add support for blackhawk cpu

Add basic CPU library code to support the Blackhawk CPU,
BlackHawk core is based out of Hunter ELP core,
so overall library code was adapted based on that.

feat(cpus): add support for blackhawk cpu

Add basic CPU library code to support the Blackhawk CPU,
BlackHawk core is based out of Hunter ELP core,
so overall library code was adapted based on that.

Change-Id: I4750e774732218ee669dceb734cd107f46b78492
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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