| 0b9f05fc | 24-Apr-2023 |
Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com> |
fix(tegra): remove dependency on CPU registers to get boot parameters
Commit 3e14df6f6 removed the code to clear the CPU registers X0 - X3, which affected the Tegra platforms. Tegra platforms rely o
fix(tegra): remove dependency on CPU registers to get boot parameters
Commit 3e14df6f6 removed the code to clear the CPU registers X0 - X3, which affected the Tegra platforms. Tegra platforms rely on the boot parameters passed through custom mechanisms and do not use these general purpose registers, but maintained sanity checks to support legacy bootloaders. These sanity checks went out of sync due to the code cleanup from bl31_entrypoint().
This patch removes the checks and calls the SOC specific handlers to retrieve the boot parameters.
Change-Id: I0cf4d9c0370c33ff7715b48592b6bc0602f3c93e Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
show more ...
|
| 48a65ec3 | 28-Apr-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(fvp): introduce PLATFORM_TEST_EA_FFH config" into integration |
| 2fd2fced | 28-Apr-2023 |
Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> |
fix(sme): disable SME for SPD=spmd
SPMD is not compatible with ENABLE_SME_FOR_NS. Hence disable SME when SPD=spmd
Change-Id: I8bcf2493819718732563f9db69f7186ac7437637 Signed-off-by: Jayanth Dodderi
fix(sme): disable SME for SPD=spmd
SPMD is not compatible with ENABLE_SME_FOR_NS. Hence disable SME when SPD=spmd
Change-Id: I8bcf2493819718732563f9db69f7186ac7437637 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
show more ...
|
| 3db998e5 | 28-Apr-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
docs: remove plat_convert_pk() interface from release doc
The code was already removed as part of commit 4ac5b3949d87 "refactor(auth): replace plat_convert_pk". The present commit just removes it fr
docs: remove plat_convert_pk() interface from release doc
The code was already removed as part of commit 4ac5b3949d87 "refactor(auth): replace plat_convert_pk". The present commit just removes it from the release documentation.
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Change-Id: I06b35f110c844267d69a865df55dd451ed2f08cd
show more ...
|
| 76b225d4 | 28-Apr-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "docs(juno): refer to SCP v2.12.0" into integration |
| 63e0b865 | 28-Apr-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
chore(io): remove io_dummy driver
In accordance with [1], delete the io_dummy driver code in preparation for the v2.9 release.
[1] https://trustedfirmware-a.readthedocs.io/en/latest/about/release-i
chore(io): remove io_dummy driver
In accordance with [1], delete the io_dummy driver code in preparation for the v2.9 release.
[1] https://trustedfirmware-a.readthedocs.io/en/latest/about/release-information.html
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Change-Id: If80573d6f889624ef06b099fd267ee85f3a6331e
show more ...
|
| baeaf292 | 28-Apr-2023 |
Okash Khawaja <okash@google.com> |
refactor(cpus): use BIT macro in a consistent manner
In assembly code, BIT macro is used with a preceding hash #. Let's update Cortex X1 code to follow the same convention. Excluding hash doesn't ca
refactor(cpus): use BIT macro in a consistent manner
In assembly code, BIT macro is used with a preceding hash #. Let's update Cortex X1 code to follow the same convention. Excluding hash doesn't cause compilation to fail or emit incorrect code.
Signed-off-by: Okash Khawaja <okash@google.com> Change-Id: If304cdf90542d2edcab3e2d66cd7e905ff7fd047
show more ...
|
| fe38cc68 | 24-Apr-2023 |
Manish Pandey <manish.pandey2@arm.com> |
feat(fvp): introduce PLATFORM_TEST_EA_FFH config
FVP currently does not have proper handler to do Firmware First Handling (FFH) of lower EL External aborts and it ends up in EL3 panic.
To test the
feat(fvp): introduce PLATFORM_TEST_EA_FFH config
FVP currently does not have proper handler to do Firmware First Handling (FFH) of lower EL External aborts and it ends up in EL3 panic.
To test the scenarios sensibly we need a proper handling when the FVP is under test so that we do not change the default behavior.
Introduce PLATFORM_TEST_EA_FFH config which will be enabled in CI scripts and implement a proper handling for Sync EA and SErrors from lower EL.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ib130154206b17f72c49c9f07de2d92f35a97ab0b
show more ...
|
| e31de867 | 28-Apr-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "fix(ras): do not put RAS check before esb macro" into integration |
| a49bb6f8 | 28-Apr-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "docs: fix a typo in the glossary" into integration |
| 1ff41ba3 | 28-Apr-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(sme): enable SME2 functionality for NS world" into integration |
| c598692d | 14-Feb-2023 |
Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
fix(qemu-sbsa): enable FGT
QEMU 7.2+ has FEAT_FGT support added to 'max' cpu.
So let's enable it to make Debian 'bookworm' kernel boot on sbsa-ref/max setup.
Signed-off-by: Marcin Juszkiewicz <mar
fix(qemu-sbsa): enable FGT
QEMU 7.2+ has FEAT_FGT support added to 'max' cpu.
So let's enable it to make Debian 'bookworm' kernel boot on sbsa-ref/max setup.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Change-Id: I49fb3e742b69ce7be5666e0144525dde21a68238
show more ...
|
| 4fba2e1f | 15-Mar-2023 |
Boyan Karatotev <boyan.karatotev@arm.com> |
chore(rme): add make rule for SPD=spmd
ENABLE_RME is set then SPD must either be spmd or it should not be set. Add a rule to assert this.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Ch
chore(rme): add make rule for SPD=spmd
ENABLE_RME is set then SPD must either be spmd or it should not be set. Add a rule to assert this.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I0556e7b0e55b04c3a8e4c20c991fbbc30486570c
show more ...
|
| a64010e4 | 15-Mar-2023 |
Boyan Karatotev <boyan.karatotev@arm.com> |
chore(bl1): remove redundant bl1_arch_next_el_setup
bl1_arch_next_el_setup has no references anywhere in TF-A. Remove it as it is redundant
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
chore(bl1): remove redundant bl1_arch_next_el_setup
bl1_arch_next_el_setup has no references anywhere in TF-A. Remove it as it is redundant
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: Ice2997f33c318390883347acdd03dc6755f87ea5
show more ...
|
| 6c42a736 | 14-Mar-2023 |
Boyan Karatotev <boyan.karatotev@arm.com> |
chore(docs): remove control register setup section
It hasn't been updated since 2017 and the documentation around that bit of code is fairly good so it is redundant to be there.
Signed-off-by: Boya
chore(docs): remove control register setup section
It hasn't been updated since 2017 and the documentation around that bit of code is fairly good so it is redundant to be there.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: Idee4523e97cb6039fae1efae35eda2b45e8f7345
show more ...
|
| 1d2706db | 06-Mar-2023 |
Boyan Karatotev <boyan.karatotev@arm.com> |
chore(pauth): remove redundant pauth_disable_el3() call
Both bl2_main and bl2_run_next_image call pauth_disable_el3. However, bl2_main is the only caller of bl2_run_next_image so it doesn't need to
chore(pauth): remove redundant pauth_disable_el3() call
Both bl2_main and bl2_run_next_image call pauth_disable_el3. However, bl2_main is the only caller of bl2_run_next_image so it doesn't need to call it
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I91769b2994ad643d2259c211936dbac4ef010d25
show more ...
|
| 7f95003b | 27-Apr-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge "build(fvp): reduce the number of cpu libraries included by default" into integration |
| b39af24f | 27-Apr-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge "style(xilinx): fix AMD copyright format" into integration |
| 03d3c0d7 | 08-Nov-2022 |
Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> |
feat(sme): enable SME2 functionality for NS world
FEAT_SME2 is an extension of FEAT_SME and an optional feature from v9.2. Its an extension of SME, wherein it not only processes matrix operations ef
feat(sme): enable SME2 functionality for NS world
FEAT_SME2 is an extension of FEAT_SME and an optional feature from v9.2. Its an extension of SME, wherein it not only processes matrix operations efficiently, but also provides outer-product instructions to accelerate matrix operations. It affords instructions for multi-vector operations. Further, it adds an 512 bit architectural register ZT0.
This patch implements all the changes introduced with FEAT_SME2 to ensure that the instructions are allowed to access ZT0 register from Non-secure lower exception levels.
Additionally, it adds support to ensure FEAT_SME2 is aligned with the existing FEATURE DETECTION mechanism, and documented.
Change-Id: Iee0f61943304a9cfc3db8f986047b1321d0a6463 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
show more ...
|
| 7d5036b8 | 27-Apr-2023 |
Manish Pandey <manish.pandey2@arm.com> |
fix(ras): do not put RAS check before esb macro
Macro esb used in TF-A executes the instruction "esb" and is kept under RAS_EXTENSION macro. RAS_EXTENSION, as it stands today, is only enabled for pl
fix(ras): do not put RAS check before esb macro
Macro esb used in TF-A executes the instruction "esb" and is kept under RAS_EXTENSION macro. RAS_EXTENSION, as it stands today, is only enabled for platforms which wants RAS errors to be handled in Firmware while esb instruction is available when RAS architecture feature is present irrespective of its handling. Currently TF-A does not have mechanism to detect whether RAS is present or not in HW, define this macro unconditionally.
Its harmless for non-RAS cores as this instruction executes as NOP.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I556f2bcf5669c378bda05909525a0a4f96c7b336
show more ...
|
| 6fc9c1cd | 27-Apr-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
docs: fix a typo in the glossary
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Change-Id: I4c76fde5e487ab4b2495f1ea692ae07f8be81d57 |
| bb5b2632 | 25-Apr-2023 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs(measured-boot): update the build command
As per recent changes to OPTEE's fvp.mk file, both options "MEASURED_BOOT" and "MEASURED_BOOT_FTPM" are required for the fTPM application to be built.
docs(measured-boot): update the build command
As per recent changes to OPTEE's fvp.mk file, both options "MEASURED_BOOT" and "MEASURED_BOOT_FTPM" are required for the fTPM application to be built.
Change-Id: I621113c3fbd47e9f5be015ea65e9b8d0f218e4e8 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
show more ...
|
| 657b90ea | 21-Apr-2023 |
Tamas Ban <tamas.ban@arm.com> |
fix(tc): enable the execution of both platform tests
The C preprocessor cannot compare defines against strings. Such an expression is always evaluated to be true. Therefore, its usage in a condition
fix(tc): enable the execution of both platform tests
The C preprocessor cannot compare defines against strings. Such an expression is always evaluated to be true. Therefore, its usage in a conditional expression results that always the first branch is taken. Other branches cannot be reached by any configuration value. The fix removes this string comparison and instead it introduces distinct defines for all the cases.
Signed-off-by: Tamas Ban <tamas.ban@arm.com> Change-Id: Ia1142b31b6778686c74e1e882fe4604fe3b6501d
show more ...
|
| d5fc8992 | 21-Apr-2023 |
Tamas Ban <tamas.ban@arm.com> |
fix(tc): update the name of mbedtls config header
Recently mbedtls_cofig.h was renamed to: - mbedtls_config-2.h - mbedtls_config-3.h
Modify the include order to resolve the static check failure i
fix(tc): update the name of mbedtls config header
Recently mbedtls_cofig.h was renamed to: - mbedtls_config-2.h - mbedtls_config-3.h
Modify the include order to resolve the static check failure in the CI.
Signed-off-by: Tamas Ban <tamas.ban@arm.com> Change-Id: I424f1cde199397b8df780a9514f1042e601c6502
show more ...
|
| 69d643c5 | 26-Apr-2023 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(ufs): poll UCRDY for all commands" into integration |