refactor(amu): use new AMU feature check routines

The AMU extension code was using its own feature detection routines.
Replace them with the generic CPU feature handlers (defined in
arch_features.h)

refactor(amu): use new AMU feature check routines

The AMU extension code was using its own feature detection routines.
Replace them with the generic CPU feature handlers (defined in
arch_features.h), which get updated to cover the v1p1 variant as well.

Change-Id: I8540f1e745d7b02a25a6c6cdf2a39d6f5e21f2aa
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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refactor(amu): unify ENABLE_AMU and ENABLE_FEAT_AMUv1

So far we have the ENABLE_AMU build option to include AMU register
handling code for enabling and context switch. There is also an
ENABLE_FEAT_A

refactor(amu): unify ENABLE_AMU and ENABLE_FEAT_AMUv1

So far we have the ENABLE_AMU build option to include AMU register
handling code for enabling and context switch. There is also an
ENABLE_FEAT_AMUv1 option, solely to protect the HAFGRTR_EL2 system
register handling. The latter needs some alignment with the new feature
scheme, but it conceptually overlaps with the ENABLE_AMU option.

Since there is no real need for two separate options, unify both into a
new ENABLE_FEAT_AMU name in a first step. This is mostly just renaming at
this point, a subsequent patch will make use of the new feature handling
scheme.

Change-Id: I97d8a55bdee2ed1e1509fa9f2b09fd0bdd82736e
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge changes from topic "xlnx_zynqmp_changes" into integration

* changes:
feat(zynqmp): build pm code as library
chore(zynqmp): print entry address to Secure and NS world

feat(zynqmp): build pm code as library

Build Platform Management(PM) code as an Library.
Building PM code as library provides an option to switch to different
firmware interfaces like custom package

feat(zynqmp): build pm code as library

Build Platform Management(PM) code as an Library.
Building PM code as library provides an option to switch to different
firmware interfaces like custom packages.

Change-Id: I872d45edf55ac83a6efb86591d12a0fef7b598cb
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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chore(zynqmp): print entry address to Secure and NS world

The base address for BL32 and BL33 is read from the FSBL to TF-A
handoff params.
Print the base address for BL32 and BL33 as entry to the se

chore(zynqmp): print entry address to Secure and NS world

The base address for BL32 and BL33 is read from the FSBL to TF-A
handoff params.
Print the base address for BL32 and BL33 as entry to the secure and
non-secure world respectively in the release build.

Change-Id: Icc976fccb56b565f78001d87b02180ced6437a43
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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Merge changes from topic "feat_state_part4" into integration

* changes:
refactor(cpufeat): enable FEAT_RNG for FEAT_STATE_CHECKED
refactor(cpufeat): align FEAT_SEL2 to new feature handling
ref

Merge changes from topic "feat_state_part4" into integration

* changes:
refactor(cpufeat): enable FEAT_RNG for FEAT_STATE_CHECKED
refactor(cpufeat): align FEAT_SEL2 to new feature handling
refactor(cpufeat): enable FEAT_NV2 for FEAT_STATE_CHECKED
refactor(cpufeat): enable FEAT_TWED for FEAT_STATE_CHECKED
refactor(cpufeat): enable FEAT_CSV2_2 for FEAT_STATE_CHECKED
refactor(cpufeat): enable FEAT_ECV for FEAT_STATE_CHECKED
refactor(cpufeat): enable FEAT_PAN for FEAT_STATE_CHECKED
refactor(cpufeat): align FEAT_SB to new feature handling
refactor(cpufeat): use alternative encoding for "SB" barrier
refactor(cpufeat): enable SYS_REG_TRACE for FEAT_STATE_CHECKED
fix(cpufeat): make stub enable functions "static inline"
fix(mpam): feat_detect: support major/minor

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Merge "docs(maintainers): add new maintainers for MediaTek SoCs" into integration

docs(maintainers): add new maintainers for MediaTek SoCs

Change-Id: Ie6afadf16921d084137b0e0b5f2a76ae504a6bc7
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>

Merge "fix(fvp): unconditionally include lib/psa headers" into integration

Merge "fix(gicv3): workaround for NVIDIA erratum T241-FABRIC-4" into integration

Merge "fix(versal-net): use spin_lock instead of bakery_lock" into integration

fix(fvp): unconditionally include lib/psa headers

Included lib/psa headers uncondiitionally to leverage their
use across different FVP build configurations.

Change-Id: I3417925e544d9ec20606a2ffba3d

fix(fvp): unconditionally include lib/psa headers

Included lib/psa headers uncondiitionally to leverage their
use across different FVP build configurations.

Change-Id: I3417925e544d9ec20606a2ffba3d46ef7adaa730
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(sc7280): add support for PSCI_OS_INIT_MODE

Enable PSCI_OS_INIT_MODE support for sc7280.

Change-Id: If94d59190c0bd876e748cd80b2641ce7616fd817
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>

feat(fvp): enable support for PSCI OS-initiated mode

Change-Id: I4cd6d2bd7ec7f581bd525d5323a3b54e855e2e51
Signed-off-by: Wing Li <wingers@google.com>

fix(gicv3): workaround for NVIDIA erratum T241-FABRIC-4

The purpose of this patch is to address the T241 erratum T241-FABRIC-4,
which causes unexpected behavior in the GIC when multiple transactions

fix(gicv3): workaround for NVIDIA erratum T241-FABRIC-4

The purpose of this patch is to address the T241 erratum T241-FABRIC-4,
which causes unexpected behavior in the GIC when multiple transactions
are received simultaneously from different sources. This hardware issue
impacts NVIDIA server platforms that use more than two T241 chips
interconnected. Each chip has support for 320 {E}SPIs.

This issue occurs when multiple packets from different GICs are
incorrectly interleaved at the target chip. The erratum text below
specifies exactly what can cause multiple transfer packets susceptible
to interleaving and GIC state corruption. GIC state corruption can
lead to a range of problems, including kernel panics, and unexpected
behavior.

Erratum documentation:
https://developer.nvidia.com/docs/t241-fabric-4/nvidia-t241-fabric-4-errata.pdf

The workaround is to ensure that MMIO accesses target the GIC on the
socket that holds the data, for example SPI ranges owned by the socket’s
GIC. This ensures that the GIC will not utilize the inter-socket AXI
Stream interface for servicing these GIC MMIO accesses.

This patch updates the functions that use the GICD_In{E} registers to
ensure that the accesses are directed to the chip that owns the SPI,
instead of using the global alias.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I04e33ba64eb306bd5fdabb56e63cbe273d8cd632

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Merge "fix(fpga): include missing header file" into integration

Merge "fix(versal-net): correct aff level for cpu off" into integration

Merge "fix(build): partially fix qemu aarch32 build" into integration

fix(rcar): add mandatory fields in 'reserved-memory' node

On the R-Car Gen3 boards, u-boot will apply this reserved-memory node
directly on the Linux device-tree.

The linux kernel requires that the

fix(rcar): add mandatory fields in 'reserved-memory' node

On the R-Car Gen3 boards, u-boot will apply this reserved-memory node
directly on the Linux device-tree.

The linux kernel requires that the ranges, #address-cells
and #size-cells values must be set in the reserved-memory node.

Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Change-Id: Ic9b9bd3f2177a224d0931f6a4f4818a87904a493

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Merge "refactor(fvp): use RSS API to retrieve attestation token and key" into integration

fix(cpus): use hint instruction for "tsb csync"

The "tsb csync" instruction is part of the Armv8.4 architecture
extension, and is not supported by many older assemblers.
We already cater for this in

fix(cpus): use hint instruction for "tsb csync"

The "tsb csync" instruction is part of the Armv8.4 architecture
extension, and is not supported by many older assemblers.
We already cater for this in lib/extensions/trbe/trbe.c, where we use
the equivalent "hint #18" encoding for this, but use the new mnemonic
in the Cortex-A510 CPU support code.

Replace "tsb csync" with the hint encoding there as well, to support
building with older binutils versions.

Change-Id: Idf39f5c6c4dbf72802c3c120047b8bc499145e3b
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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fix(fpga): include missing header file

Since transitioning over FEAT_SPE to the new feature checking scheme, we
make use of the new is_feat_spe_supported() function in the Arm FPGA
platform code. Ho

fix(fpga): include missing header file

Since transitioning over FEAT_SPE to the new feature checking scheme, we
make use of the new is_feat_spe_supported() function in the Arm FPGA
platform code. However this missed to include the header file, so the
build broke.

Add the arch_features.h header to make arm_fpga compile again.

Change-Id: I5c8feecfcc6fb5845a6671842850df1943086a58
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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fix(versal-net): use spin_lock instead of bakery_lock

In ARM v8.2 the cache will turn off automatically when cpu power down.
Therefore use the spin_lock instead of bakery_lock for the platform in
wh

fix(versal-net): use spin_lock instead of bakery_lock

In ARM v8.2 the cache will turn off automatically when cpu power down.
Therefore use the spin_lock instead of bakery_lock for the platform in
which HW_ASSISTED_COHERENCY is enabled.

In Versal NET platform HW_ASSISTED_COHERENCY is enabled so it will use
spin lock. In ZynqMP and Versal HW_ASSISTED_COHERENCY is not enabled so
it will use bakery_lock.

Also remove bakery_lock_init() because it is empty.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I18ff939b51f16d7d3484d8564d6ee6c586f363d8

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fix(versal-net): correct aff level for cpu off

CPU suspend is calling validate_power_state PSCI opps which returns
power domain state for CPU suspend according to PSTATE type. In case of
power down

fix(versal-net): correct aff level for cpu off

CPU suspend is calling validate_power_state PSCI opps which returns
power domain state for CPU suspend according to PSTATE type. In case of
power down it assigns PLAT_MAX_OFF_STATE to all affinity level which is
incorrect since for CPU suspend we need to set only MPIDR_AFFLVL0 which
is CPU state. So correct affinity level for CPU suspend.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I39f92790ea74e4cab8e87342e73e1ac211a46fcd

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fix(build): partially fix qemu aarch32 build

While aarch32 isn't currently supported on qemu, platform.mk contains
hard-coded references to aarch64 in BL1_SOURCES which should be ${ARCH}.

This impr

fix(build): partially fix qemu aarch32 build

While aarch32 isn't currently supported on qemu, platform.mk contains
hard-coded references to aarch64 in BL1_SOURCES which should be ${ARCH}.

This improves the situation, but since aarch32/qemu_max.S doesn't exist
and there are other missing files for aarch32, this is only a partial
fix.

Signed-off-by: Rebecca Cran <rebecca@quicinc.com>
Change-Id: I3fa01483e572abfd781ceaecff16ecf57cda8316

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