fix(fvp): incorrect UUID name in FVP tb_fw_config

Signed-off-by: Rob Hughes <robert.hughes@arm.com>
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I557bca7dd32c3be084bbba11d84dfa281

fix(fvp): incorrect UUID name in FVP tb_fw_config

Signed-off-by: Rob Hughes <robert.hughes@arm.com>
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I557bca7dd32c3be084bbba11d84dfa2818cb6791

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fix(ethos-n): add workaround for erratum 2838783

To workaround Arm(R) Ethos(TM)-N NPU erratum 2838783, the NPU has been
configured to allow being woken up by both secure and non-secure events
to mak

fix(ethos-n): add workaround for erratum 2838783

To workaround Arm(R) Ethos(TM)-N NPU erratum 2838783, the NPU has been
configured to allow being woken up by both secure and non-secure events
to make sure that an event always wakes up the NPU.

The API version has been given a minor version bump with this change to
indicate that this fix is included.

Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I429cdd6bf1e633b4dedf2e94af28937dd892a0ba

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feat(ethos-n): add support for NPU to cert_create

Add Juno specific Makefile to the certificate tool build. That
Makefile is included by the certificate tool Makefile to add
information about the au

feat(ethos-n): add support for NPU to cert_create

Add Juno specific Makefile to the certificate tool build. That
Makefile is included by the certificate tool Makefile to add
information about the authentication data for the
Arm(R) Ethos(TM)-N NPU's firmware binary.

Signed-off-by: Mohamed Elzahhar <Mohamed.Elzahhar@arm.com>
Signed-off-by: Rob Hughes <robert.hughes@arm.com>
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: Ie4b6a1c29d73b3ed5041b57f2cd88033be18a63a

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feat(ethos-n): add NPU support in fiptool

Add platform specific Makefile to add UUIDs and command options
for the Arm(R) Ethos(TM)-N NPU firmware binary and certificate
data to the FIP so that the T

feat(ethos-n): add NPU support in fiptool

Add platform specific Makefile to add UUIDs and command options
for the Arm(R) Ethos(TM)-N NPU firmware binary and certificate
data to the FIP so that the TF-A's BL2 can later be used to load
the Arm(R) Ethos(TM)-N NPU firmware binary into memory and verify
its integrity.

Add separate driver specific include header file for the
Arm(R) Ethos(TM)-N NPU images containing UUIDs and command options
to make it easy to port the FIP support to other platforms.

Signed-off-by: Daniele Castro <daniele.castro@arm.com>
Signed-off-by: Rob Hughes <robert.hughes@arm.com>
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I8cd64fb20d58f8bd539facb085606213d6cead05

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feat(ethos-n): add support to set up NSAID

For the TZC to allow the Arm(R) Ethos(TM)-N NPU to access the buffers
allocated in a protected memory region, it must include the correct
NSAID for that re

feat(ethos-n): add support to set up NSAID

For the TZC to allow the Arm(R) Ethos(TM)-N NPU to access the buffers
allocated in a protected memory region, it must include the correct
NSAID for that region in its transactions to the memory. This change
updates the SiP service to configure the NSAIDs specified by a platform
define. When doing a protected access the SiP service now configures the
NSAIDs specified by the platform define. For unprotected access the
NSAID is set to zero.

Signed-off-by: Rajasekaran Kalidoss <rajasekaran.kalidoss@arm.com>
Signed-off-by: Rob Hughes <robert.hughes@arm.com>
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I3360ef33705162aba5c67670386922420869e331

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build(fiptool): add object dependency generation

The object target in the fiptool Makefile only depends on the
corresponding source file so it won't rebuild the object, if a header
file used by the

build(fiptool): add object dependency generation

The object target in the fiptool Makefile only depends on the
corresponding source file so it won't rebuild the object, if a header
file used by the source file is changed.

To make it rebuild the object file for both source and header file
changes, a dependency file will now be generated for each object and
included in the Makefile.

Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I0468c6e9c54126242150667268d471f28e011b0d

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feat(ethos-n): add NPU sleeping SMC call

The non-secure world delegation of the register needed to determine if
the Arm(R) Ethos(TM)-N NPU is active or sleeping will be removed in the
future. In pre

feat(ethos-n): add NPU sleeping SMC call

The non-secure world delegation of the register needed to determine if
the Arm(R) Ethos(TM)-N NPU is active or sleeping will be removed in the
future. In preparation for the change, a new SMC call has been added to
allow the non-secure world to ask the SiP service for the state instead.

A minor API version bump has been done with this change to indicate
support for the new functionality.

Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I1338341be385cf1891f4809efb7083fae6d928bc

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feat(ethos-n): add multiple asset allocators

Adds additional asset allocators to the device tree include
file as the non-secure world kernel module for the Arm(R)
Ethos(TM)-N NPU now fully supports

feat(ethos-n): add multiple asset allocators

Adds additional asset allocators to the device tree include
file as the non-secure world kernel module for the Arm(R)
Ethos(TM)-N NPU now fully supports having and using multiple
asset allocators.

Signed-off-by: Joshua Pimm <joshua.pimm@arm.com>
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I82d53667ef64968ee814f611d0a90abd3b3cf3de

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feat(ethos-n): add reset type to reset SMC calls

Adds a reset type argument for the soft and hard reset SMC calls to
indicate whether to perform a full reset and setup or only halt the
Arm(R) Ethos(

feat(ethos-n): add reset type to reset SMC calls

Adds a reset type argument for the soft and hard reset SMC calls to
indicate whether to perform a full reset and setup or only halt the
Arm(R) Ethos(TM)-N NPU. For use in cases where the NPU will not be
used but must be put into a known state, such as suspending the NPU
as part of power management.

Signed-off-by: Joshua Pimm <joshua.pimm@arm.com>
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I6018af85a28b0e977166ec29d26f04739123140c

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feat(ethos-n): add protected NPU TZMP1 regions

TZMP1 protected memory regions have been added in the Juno platform to
store sensitive data for the Arm(R) Ethos(TM)-N NPU
This is enabled when buildin

feat(ethos-n): add protected NPU TZMP1 regions

TZMP1 protected memory regions have been added in the Juno platform to
store sensitive data for the Arm(R) Ethos(TM)-N NPU
This is enabled when building TF-A with ARM_ETHOSN_NPU_TZMP1.

The NPU uses two protected memory regions:
1) Firmware region to protect the NPU's firmware from being modified
from the non-secure world
2) Data region for sensitive data used by the NPU

Respective memory region can only be accessed with their unique NSAID.

Signed-off-by: Bjorn Engstrom <bjoern.engstroem@arm.com>
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Signed-off-by: Rob Hughes <robert.hughes@arm.com>
Change-Id: I65200047f10364ca18681ce348a6edb2ffb9b095

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build(ethos-n): add TZMP1 build flag

For the Arm(R) Ethos(TM)-N NPU Driver to support running inference with
protected memory the TZC must be configured with appropriate regions.

This is controlled

build(ethos-n): add TZMP1 build flag

For the Arm(R) Ethos(TM)-N NPU Driver to support running inference with
protected memory the TZC must be configured with appropriate regions.

This is controlled in build time by the now added build flag.

The new build flag is only supported with the Arm Juno platform and the
TZC is configured with default memory regions as if TZMP1 wasn't
enabled to facilitate adding the new memory regions later.

Signed-off-by: Bjorn Engstrom <bjoern.engstroem@arm.com>
Signed-off-by: Rob Hughes <robert.hughes@arm.com>
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I9dc49ac5d091cfbc8c20d7c3ab394a2836438b0f

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Merge "fix(fvp): work around BL31 progbits exceeded" into integration

fix(fvp): work around BL31 progbits exceeded

It is useful to have a single build for the FVP that includes as much
stuff as possible. Such a build allows a single TF-A build to be used on
a wide var

fix(fvp): work around BL31 progbits exceeded

It is useful to have a single build for the FVP that includes as much
stuff as possible. Such a build allows a single TF-A build to be used on
a wide variety of fvp command lines. Unfortunately, the fvp also has a
(somewhat arbitrary) SRAM limit and enabling a bunch of stuff overruns
what is available.

To workaround this limit, don't enable everything for all
configurations. The offending configuration is when tsp is enabled, so
try to slim the binary down only when building with it.

As this doesn't solve the issue of running out of space for BL31, update
the linker error to give some clue as to what has (likely) caused it
while more permanent fixes are found.

Also add FEAT_RNG to the mix as it got missed in the commotion.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Icb27cc837c2d90ca182693e9b3121b51383d51fd

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Merge "docs(sve): update defaults for FEAT_SVE" into integration

Merge changes from topic "jc/sve" into integration

* changes:
fix(qemu): enable dynamic feature detection of FEAT_SVE for NormalWorld
fix(tc): enable dynamic feature detection of FEAT_SVE for No

Merge changes from topic "jc/sve" into integration

* changes:
fix(qemu): enable dynamic feature detection of FEAT_SVE for NormalWorld
fix(tc): enable dynamic feature detection of FEAT_SVE for NormalWorld

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docs(sve): update defaults for FEAT_SVE

FEAT_SVE build macro, "ENABLE_SVE_FOR_NS" default value has been updated
to 2, to support its existing behavior of dynamic detection as well as
keep it aligne

docs(sve): update defaults for FEAT_SVE

FEAT_SVE build macro, "ENABLE_SVE_FOR_NS" default value has been updated
to 2, to support its existing behavior of dynamic detection as well as
keep it aligned with the changes concerning STATE=FEAT_STATE_CHECKED(2),
part of Feature Detection procedure.

Change-Id: Iee43e899f19dc9d5eb57c235998758f462a8c397
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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fix(qemu): enable dynamic feature detection of FEAT_SVE for NormalWorld

Currently, TF-A supports three states for feature flags:
0: FEAT_DISABLED
1: FEAT_STATE_ALWAYS ( for fixed/real platforms)
2:

fix(qemu): enable dynamic feature detection of FEAT_SVE for NormalWorld

Currently, TF-A supports three states for feature flags:
0: FEAT_DISABLED
1: FEAT_STATE_ALWAYS ( for fixed/real platforms)
2: FEAT_STATE_CHECK ( for configurable platforms)
to meet the feature detection requirements dynamically, mainly
targetting configurable/Fixed Virtual platforms.

With this mechanism in place, we are refactoring all the existing
feature flags to the FEAT_STATE_CHECK option(=2), including
FEAT_SVE explicitly for FVPs.

SVE Patch Reference:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/19888/25

This newly introduced change, breaks the existing behaviour especially
for virtual platforms, who have set the ENABLE_SVE_FOR_NS flag to 1.

Moving ahead, we advise the platforms to take the following steps while
enabling the features:

1. If the platform is configurable (virtual), and want to ensure feature
detection happens dynamically at runtime, set the build flags to
FEAT_STATE_CHECK(=2).

2. For real(fixed) platforms, depending on the features supported by the
hardware and platform wants to enable it, platforms could set build
flags to FEAT_STATE_ALWAYS(=1).

(Note: Only the non-secure world enablement related build flags have
been refactored to take the values within 0 to 2. As earlier Secure
world enablement flags will still remain boolean.)

Henceforth, in order to keep it aligned with this tri-state mechanism,
changing the qemu platform default to the now supported dynamic
option(=2), so the right decision can be made by the code at runtime.

Change-Id: Icc95b8b872378b7874d4345b631adfc314e4dada
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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fix(tc): enable dynamic feature detection of FEAT_SVE for NormalWorld

Currently, TF-A supports three states for feature flags:
0: FEAT_DISABLED
1: FEAT_STATE_ALWAYS (for fixed/real platforms)
2: FEA

fix(tc): enable dynamic feature detection of FEAT_SVE for NormalWorld

Currently, TF-A supports three states for feature flags:
0: FEAT_DISABLED
1: FEAT_STATE_ALWAYS (for fixed/real platforms)
2: FEAT_STATE_CHECK (for configurable platforms)
to meet the feature detection requirements dynamically, mainly
targetting configurable/Fixed Virtual platforms.

With this mechanism in place, we are refactoring all the existing
feature flags to the FEAT_STATE_CHECK option(=2), including
FEAT_SVE explicitly for FVPs.

SVE Patch Reference:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/19888/25

This newly introduced change, breaks the existing behaviour especially
for virtual platforms, who have set the ENABLE_SVE_FOR_NS flag to 1.

Moving ahead, we advise the platforms to take the following steps while
enabling the features:

1. If the platform is configurable (virtual), and want to ensure feature
detection happens dynamically at runtime, set the build flags to
FEAT_STATE_CHECK(=2).

2. For real(fixed) platforms, depending on the features supported by the
hardware and platform wants to enable it, platforms could set build
flags to FEAT_STATE_ALWAYS(=1).

(Note: Only the non-secure world enablement related build flags have
been refactored to take the values within 0 to 2. As earlier Secure
world enablement flags will still remain boolean.)

Henceforth, in order to keep it aligned with this tri-state mechanism,
changing the TC platform default to the now supported dynamic
option(=2), so the right decision can be made by the code at runtime.

Change-Id: I4c1ebeb55a00a7f148fac1573a6694b7c02a0a81
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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Merge changes I6b4a4d22,I06bde289,I86e39481,I7ea9b75c into integration

* changes:
feat(stm32mp1-fdts): use /omit-if-no-ref/ for pins nodes
feat(st): mandate dtc version 1.4.7
refactor(st): mov

Merge changes I6b4a4d22,I06bde289,I86e39481,I7ea9b75c into integration

* changes:
feat(stm32mp1-fdts): use /omit-if-no-ref/ for pins nodes
feat(st): mandate dtc version 1.4.7
refactor(st): move mbedtls config files
refactor(st): add common mk files

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feat(ti): synchronize access to secure proxy threads

When communicating with the system controller over secure proxy we clear
a thread, write our message, then wait for a response. This must not be

feat(ti): synchronize access to secure proxy threads

When communicating with the system controller over secure proxy we clear
a thread, write our message, then wait for a response. This must not be
interrupted by a different transfer on the same thread. Take a lock
during this sequence to prevent contention.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I7789f017fde7180ab6b4ac07458464b967c8e580

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refactor(ti): remove inline directive from ti_sci and sec_proxy drivers

Let the compiler choose when to inline. Here this reduces binary size.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I6

refactor(ti): remove inline directive from ti_sci and sec_proxy drivers

Let the compiler choose when to inline. Here this reduces binary size.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I68cd0fc3a94c8c94781ca3dc277a1dd4c6f2bd3a

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refactor(ti): refactor ti_sci_{setup,do}_xfer to allow zero size response

This allows us to use the common xfer setup path even for no-wait
messages. Then factor that out of each no-wait function.

refactor(ti): refactor ti_sci_{setup,do}_xfer to allow zero size response

This allows us to use the common xfer setup path even for no-wait
messages. Then factor that out of each no-wait function.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Ib17d3facd293f3fc91dda56b2906121b43250261

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feat(ti): add sub and patch version number support

Although we do not use these for anything today, they are returned
in this structure and the struct's definition should match.

While here fix a co

feat(ti): add sub and patch version number support

Although we do not use these for anything today, they are returned
in this structure and the struct's definition should match.

While here fix a couple comment typos.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Iac4ec999b44e703e600bde93b0eee83753566876

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Merge "fix(aarch64): allow build with ARM_ARCH_MINOR=4" into integration

fix(aarch64): allow build with ARM_ARCH_MINOR=4

When building the FVP platform with SPMD (which activates the context
switch code), but keeping ARM_ARCH_MINOR to 4 or lower, the assembler
will compl

fix(aarch64): allow build with ARM_ARCH_MINOR=4

When building the FVP platform with SPMD (which activates the context
switch code), but keeping ARM_ARCH_MINOR to 4 or lower, the assembler
will complain about the SCXTNUM_EL2 system register not being supported
by the "selected processor".

Allow building this combination of options by defining the SCXTNUM_EL2
register via the generic S3_ encoding, so any assembler, with any -march
settings, will generate the access without any warnings.

We do protect accesses to this register by runtime checks, if not
explicitly requested otherwise, so can override the toolchain in this
case.

Change-Id: I0941f4c4dcf541bd968c153b9c3fac61ca23f7ef
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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