style(msm8916): add missing braces to while statements

According to the coding style all conditional statements (such as if,
for, while, do) must use braces regardless of the number of the
statement

style(msm8916): add missing braces to while statements

According to the coding style all conditional statements (such as if,
for, while, do) must use braces regardless of the number of the
statements in the body [1].

Fix this for the code inside plat/qti/msm8916.

[1]: https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-style.html#conditional-statement-bodies

Change-Id: I74f2e65aa2b3a65899e37dfd3f481d90fb15531c
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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Merge "fix(spmd): perform G0 interrupt acknowledge and deactivation" into integration

Merge "refactor(tc): move all plat tests in test makefile" into integration

Merge changes from topics "rotpk_rss_interface", "rss_interfaces" into integration

* changes:
refactor(tc): print RSS interface test PSA status
test(tc): test for AP/RSS interface for ROTPK
fe

Merge changes from topics "rotpk_rss_interface", "rss_interfaces" into integration

* changes:
refactor(tc): print RSS interface test PSA status
test(tc): test for AP/RSS interface for ROTPK
feat(psa): interface with RSS for retrieving ROTPK

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refactor(cpus): reorder Neoverse-N1 .S file

Moving neoverse_n1_disable_speculative_loads function before reset
function to maintain git blame with refactor to new framework.

Change-Id: I79a4de9955a

refactor(cpus): reorder Neoverse-N1 .S file

Moving neoverse_n1_disable_speculative_loads function before reset
function to maintain git blame with refactor to new framework.

Change-Id: I79a4de9955a6f37e289456a743b946c0c4c8c27f
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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refactor(cpus): convert Neoverse-E1 to framework

For E1, this involves replacing:
- The reset_func with the standard cpu_reset_func_{start,end}
to apply errata automatically
- The <cpu>_erra

refactor(cpus): convert Neoverse-E1 to framework

For E1, this involves replacing:
- The reset_func with the standard cpu_reset_func_{start,end}
to apply errata automatically
- The <cpu>_errata_report with the errata_report_shim to
report errata automatically
And for the E1 DSU erratum, creating symbolic names to the already
existing errata workaround functions to get them registered under
the Errata Framework.

Testing was conducted by:
- Manual comparison of disassembly of converted functions with non-
converted functions:

aarch64-none-elf-objdump -D
<trusted-firmware-a with conversion>/build/fvp/release/bl31/bl31.elf
vs
aarch64-none-elf-objdump -D
<trusted-firmware-a clean repo>/build/fvp/release/bl31/bl31.elf

- Build for debug with all errata enabled and step through ArmDS
to ensure all functions are entered and the path remains the same
as before conversion to the new framework.

Change-Id: I0a059574948badbd108333344286c76aeb142e71
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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refactor(tc): move all plat tests in test makefile

Moving all PLATFORM_TESTS into platform test makefile

Change-Id: I31821e9e69d916d12ae4c804df26f07fb523c835
Signed-off-by: Lauren Wehrmeister <laur

refactor(tc): move all plat tests in test makefile

Moving all PLATFORM_TESTS into platform test makefile

Change-Id: I31821e9e69d916d12ae4c804df26f07fb523c835
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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fix(spmd): perform G0 interrupt acknowledge and deactivation

Prior to delegating handling of Group0 secure interrupt to platform
handler, SPMD framework must acknowledge the highest pending interrup

fix(spmd): perform G0 interrupt acknowledge and deactivation

Prior to delegating handling of Group0 secure interrupt to platform
handler, SPMD framework must acknowledge the highest pending interrupt.
Moreover, once the platform has handled the interrupt successfully,
SPMD must deactivate the interrupt.

The rationale behind this decision is SPMD framework is well suited to
perform interrupt management at GIC boundary while the platform handler
is well equipped to deal with the device interface related to the
interrupt.

This patch also fixes a bug in the error code returned upon invocation
of FFA_EL3_INTR_HANDLE from normal world.

Change-Id: If8fef51899e25f966038cc01ec58c84ee25e88eb
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge changes from topic "bk/context_refactor" into integration

* changes:
refactor(amu): separate the EL2 and EL3 enablement code
refactor(cpufeat): separate the EL2 and EL3 enablement code

refactor(tc): print RSS interface test PSA status

Adding PSA status to print statement upon failing communication
initialization, non-volatile counter, and rotpk read interface calls in
platform_tes

refactor(tc): print RSS interface test PSA status

Adding PSA status to print statement upon failing communication
initialization, non-volatile counter, and rotpk read interface calls in
platform_tests.

Change-Id: Ia949cc2d18e93efb68f663d0c4e5500ca9021a94
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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test(tc): test for AP/RSS interface for ROTPK

Adding new test for AP/RSS interface for reading ROTPK for
each 3 types of ROTPKs for: CCA, secure, and non-secure firmware.

Enabled by PLATFORM_TEST=r

test(tc): test for AP/RSS interface for ROTPK

Adding new test for AP/RSS interface for reading ROTPK for
each 3 types of ROTPKs for: CCA, secure, and non-secure firmware.

Enabled by PLATFORM_TEST=rss-rotpk.

Update to print output when AP/RSS interface platform tests
pass to be able to reuse expect script functionality in CI.

Change-Id: Icc50b090e18a272378751fda104d209738b5b70c
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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Merge "docs: move common build option from Arm-specific to common file" into integration

feat(psa): interface with RSS for retrieving ROTPK

Adding the AP/RSS interface for reading the ROTPK.

The read interface implements the psa_call:
psa_call(RSS_CRYPTO_HANDLE, PSA_IPC_CALL,

feat(psa): interface with RSS for retrieving ROTPK

Adding the AP/RSS interface for reading the ROTPK.

The read interface implements the psa_call:
psa_call(RSS_CRYPTO_HANDLE, PSA_IPC_CALL,
in_vec, IOVEC_LEN(in_vec),
out_vec, IOVEC_LEN(out_vec));

where the in_vec indicates which of the 3 ROTPKs we want,
and the out_vec stores the ROTPK value we get back from RSS.

Through this service, we will be able to read any of the 3
ROTPKs used on a CCA platform:
- ROTPK for CCA firmware (BL2, BL31, RMM).
- ROTPK for secure firmware.
- ROTPK for non-secure firmware.

Change-Id: I44c615588235cc797fdf38870b74b4c422be0a72
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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Merge "feat(libc): add %X to printf/snprintf" into integration

Merge "feat(mt8188): modify APU DAPC permission" into integration

Merge changes from topic "xlnx_dtb_modification" into integration

* changes:
feat(versal-net): ddr address reservation in dtb at runtime
feat(versal): ddr address reservation in dtb at runtime

chore(ethos-n): update npu firmware version

A newer version of the Arm(R) Ethos(TM)-N NPU firmware is now available,
and so the constants in the SiP service need updating.

Change-Id: I8eee7d543bac0

chore(ethos-n): update npu firmware version

A newer version of the Arm(R) Ethos(TM)-N NPU firmware is now available,
and so the constants in the SiP service need updating.

Change-Id: I8eee7d543bac0a726c6161a16b3df90609f6b443
Signed-off-by: Rob Hughes <robert.hughes@arm.com>

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Merge "fix(xlat): fix defects on the xlat library reported by coverity scan" into integration

feat(mt8188): modify APU DAPC permission

We limited the r/w permission of some register groups for security
concerns. These regitser groups should not be accessed by domain 3 or
domain 5.

Change-Id

feat(mt8188): modify APU DAPC permission

We limited the r/w permission of some register groups for security
concerns. These regitser groups should not be accessed by domain 3 or
domain 5.

Change-Id: I2188da88d9e10a931d87bda14dc7dca46633dcd8
Signed-off-by: Chungying Lu <chungying.lu@mediatek.corp-partner.google.com>

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feat(libc): add %X to printf/snprintf

Enables printing captial hex chars as well as lowercase

Change-Id: I4dc48c3db97b908f0bb344d7765807967de8cf02
Signed-off-by: Matt Schulte <matsch@google.com>

fix(xlat): fix defects on the xlat library reported by coverity scan

The coverity defects fixed by this patch is

** CID 394601: Integer handling issues (NO_EFFECT)
/lib/xlat_tables_v2/aarch64/xla

fix(xlat): fix defects on the xlat library reported by coverity scan

The coverity defects fixed by this patch is

** CID 394601: Integer handling issues (NO_EFFECT)
/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c: 30 in
xlat_arch_is_granule_size_supported()

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: Ibc8e20bd7318a52702fbd7aa86e22cd2ded42610

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Merge "build(fpga): remove a710 from fpga build" into integration

Merge changes from topic "master" into integration

* changes:
fix(tc): rename macro to match PSA spec
fix(tc): Correct return type

feat(versal-net): ddr address reservation in dtb at runtime

When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.

A new build

feat(versal-net): ddr address reservation in dtb at runtime

When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.

A new build time parameter, XILINX_OF_BOARD_DTB_ADDR, is introduced.
The TF-A will reserve the DDR memory only when a valid DTB address
is provided to XILINX_OF_BOARD_DTB_ADDR during build.

Now the user has options, either manually reserve the desired DDR
address range for TF-A in device tree or let TF-A access and modify
the device tree, to reserve the DDR address range, in runtime using
the build parameter.

Change-Id: I45a5d9a8343ea8a19ea014a70023731de94d061a
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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feat(versal): ddr address reservation in dtb at runtime

When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.

A new build tim

feat(versal): ddr address reservation in dtb at runtime

When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.

A new build time parameter, XILINX_OF_BOARD_DTB_ADDR, is introduced.
The TF-A will reserve the DDR memory only when a valid DTB address
is provided to XILINX_OF_BOARD_DTB_ADDR during build.

Now the user has options, either manually reserve the desired DDR
address range for TF-A in device tree or let TF-A access and modify
the device tree, to reserve the DDR address range, in runtime using
the build parameter.

Change-Id: I4442a90e1cab5a3a115f4eeb8a7e09e247189ff0
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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