1/* 2 * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cpuamu.h> 10#include <cpu_macros.S> 11#include <neoverse_n1.h> 12#include "wa_cve_2022_23960_bhb_vector.S" 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Neoverse N1 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Neoverse-N1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24 .global neoverse_n1_errata_ic_trap_handler 25 26#if WORKAROUND_CVE_2022_23960 27 wa_cve_2022_23960_bhb_vector_table NEOVERSE_N1_BHB_LOOP_COUNT, neoverse_n1 28#endif /* WORKAROUND_CVE_2022_23960 */ 29 30/* -------------------------------------------------- 31 * Errata Workaround for Neoverse N1 Erratum 1043202. 32 * This applies to revision r0p0 and r1p0 of Neoverse N1. 33 * Inputs: 34 * x0: variant[4:7] and revision[0:3] of current cpu. 35 * Shall clobber: x0-x17 36 * -------------------------------------------------- 37 */ 38func errata_n1_1043202_wa 39 /* Compare x0 against revision r1p0 */ 40 mov x17, x30 41 bl check_errata_1043202 42 cbz x0, 1f 43 44 /* Apply instruction patching sequence */ 45 ldr x0, =0x0 46 msr CPUPSELR_EL3, x0 47 ldr x0, =0xF3BF8F2F 48 msr CPUPOR_EL3, x0 49 ldr x0, =0xFFFFFFFF 50 msr CPUPMR_EL3, x0 51 ldr x0, =0x800200071 52 msr CPUPCR_EL3, x0 53 isb 541: 55 ret x17 56endfunc errata_n1_1043202_wa 57 58func check_errata_1043202 59 /* Applies to r0p0 and r1p0 */ 60 mov x1, #0x10 61 b cpu_rev_var_ls 62endfunc check_errata_1043202 63 64/* -------------------------------------------------- 65 * Errata Workaround for Neoverse N1 Errata #1073348 66 * This applies to revision r0p0 and r1p0 of Neoverse N1. 67 * Inputs: 68 * x0: variant[4:7] and revision[0:3] of current cpu. 69 * Shall clobber: x0-x17 70 * -------------------------------------------------- 71 */ 72func errata_n1_1073348_wa 73 /* Compare x0 against revision r1p0 */ 74 mov x17, x30 75 bl check_errata_1073348 76 cbz x0, 1f 77 mrs x1, NEOVERSE_N1_CPUACTLR_EL1 78 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6 79 msr NEOVERSE_N1_CPUACTLR_EL1, x1 801: 81 ret x17 82endfunc errata_n1_1073348_wa 83 84func check_errata_1073348 85 /* Applies to r0p0 and r1p0 */ 86 mov x1, #0x10 87 b cpu_rev_var_ls 88endfunc check_errata_1073348 89 90/* -------------------------------------------------- 91 * Errata Workaround for Neoverse N1 Errata #1130799 92 * This applies to revision <=r2p0 of Neoverse N1. 93 * Inputs: 94 * x0: variant[4:7] and revision[0:3] of current cpu. 95 * Shall clobber: x0-x17 96 * -------------------------------------------------- 97 */ 98func errata_n1_1130799_wa 99 /* Compare x0 against revision r2p0 */ 100 mov x17, x30 101 bl check_errata_1130799 102 cbz x0, 1f 103 mrs x1, NEOVERSE_N1_CPUACTLR2_EL1 104 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 105 msr NEOVERSE_N1_CPUACTLR2_EL1, x1 1061: 107 ret x17 108endfunc errata_n1_1130799_wa 109 110func check_errata_1130799 111 /* Applies to <=r2p0 */ 112 mov x1, #0x20 113 b cpu_rev_var_ls 114endfunc check_errata_1130799 115 116/* -------------------------------------------------- 117 * Errata Workaround for Neoverse N1 Errata #1165347 118 * This applies to revision <=r2p0 of Neoverse N1. 119 * Inputs: 120 * x0: variant[4:7] and revision[0:3] of current cpu. 121 * Shall clobber: x0-x17 122 * -------------------------------------------------- 123 */ 124func errata_n1_1165347_wa 125 /* Compare x0 against revision r2p0 */ 126 mov x17, x30 127 bl check_errata_1165347 128 cbz x0, 1f 129 mrs x1, NEOVERSE_N1_CPUACTLR2_EL1 130 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 131 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 132 msr NEOVERSE_N1_CPUACTLR2_EL1, x1 1331: 134 ret x17 135endfunc errata_n1_1165347_wa 136 137func check_errata_1165347 138 /* Applies to <=r2p0 */ 139 mov x1, #0x20 140 b cpu_rev_var_ls 141endfunc check_errata_1165347 142 143/* -------------------------------------------------- 144 * Errata Workaround for Neoverse N1 Errata #1207823 145 * This applies to revision <=r2p0 of Neoverse N1. 146 * Inputs: 147 * x0: variant[4:7] and revision[0:3] of current cpu. 148 * Shall clobber: x0-x17 149 * -------------------------------------------------- 150 */ 151func errata_n1_1207823_wa 152 /* Compare x0 against revision r2p0 */ 153 mov x17, x30 154 bl check_errata_1207823 155 cbz x0, 1f 156 mrs x1, NEOVERSE_N1_CPUACTLR2_EL1 157 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 158 msr NEOVERSE_N1_CPUACTLR2_EL1, x1 1591: 160 ret x17 161endfunc errata_n1_1207823_wa 162 163func check_errata_1207823 164 /* Applies to <=r2p0 */ 165 mov x1, #0x20 166 b cpu_rev_var_ls 167endfunc check_errata_1207823 168 169/* -------------------------------------------------- 170 * Errata Workaround for Neoverse N1 Errata #1220197 171 * This applies to revision <=r2p0 of Neoverse N1. 172 * Inputs: 173 * x0: variant[4:7] and revision[0:3] of current cpu. 174 * Shall clobber: x0-x17 175 * -------------------------------------------------- 176 */ 177func errata_n1_1220197_wa 178 /* Compare x0 against revision r2p0 */ 179 mov x17, x30 180 bl check_errata_1220197 181 cbz x0, 1f 182 mrs x1, NEOVERSE_N1_CPUECTLR_EL1 183 orr x1, x1, NEOVERSE_N1_WS_THR_L2_MASK 184 msr NEOVERSE_N1_CPUECTLR_EL1, x1 1851: 186 ret x17 187endfunc errata_n1_1220197_wa 188 189func check_errata_1220197 190 /* Applies to <=r2p0 */ 191 mov x1, #0x20 192 b cpu_rev_var_ls 193endfunc check_errata_1220197 194 195/* -------------------------------------------------- 196 * Errata Workaround for Neoverse N1 Errata #1257314 197 * This applies to revision <=r3p0 of Neoverse N1. 198 * Inputs: 199 * x0: variant[4:7] and revision[0:3] of current cpu. 200 * Shall clobber: x0-x17 201 * -------------------------------------------------- 202 */ 203func errata_n1_1257314_wa 204 /* Compare x0 against revision r3p0 */ 205 mov x17, x30 206 bl check_errata_1257314 207 cbz x0, 1f 208 mrs x1, NEOVERSE_N1_CPUACTLR3_EL1 209 orr x1, x1, NEOVERSE_N1_CPUACTLR3_EL1_BIT_10 210 msr NEOVERSE_N1_CPUACTLR3_EL1, x1 2111: 212 ret x17 213endfunc errata_n1_1257314_wa 214 215func check_errata_1257314 216 /* Applies to <=r3p0 */ 217 mov x1, #0x30 218 b cpu_rev_var_ls 219endfunc check_errata_1257314 220 221/* -------------------------------------------------- 222 * Errata Workaround for Neoverse N1 Errata #1262606 223 * This applies to revision <=r3p0 of Neoverse N1. 224 * Inputs: 225 * x0: variant[4:7] and revision[0:3] of current cpu. 226 * Shall clobber: x0-x17 227 * -------------------------------------------------- 228 */ 229func errata_n1_1262606_wa 230 /* Compare x0 against revision r3p0 */ 231 mov x17, x30 232 bl check_errata_1262606 233 cbz x0, 1f 234 mrs x1, NEOVERSE_N1_CPUACTLR_EL1 235 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13 236 msr NEOVERSE_N1_CPUACTLR_EL1, x1 2371: 238 ret x17 239endfunc errata_n1_1262606_wa 240 241func check_errata_1262606 242 /* Applies to <=r3p0 */ 243 mov x1, #0x30 244 b cpu_rev_var_ls 245endfunc check_errata_1262606 246 247/* -------------------------------------------------- 248 * Errata Workaround for Neoverse N1 Errata #1262888 249 * This applies to revision <=r3p0 of Neoverse N1. 250 * Inputs: 251 * x0: variant[4:7] and revision[0:3] of current cpu. 252 * Shall clobber: x0-x17 253 * -------------------------------------------------- 254 */ 255func errata_n1_1262888_wa 256 /* Compare x0 against revision r3p0 */ 257 mov x17, x30 258 bl check_errata_1262888 259 cbz x0, 1f 260 mrs x1, NEOVERSE_N1_CPUECTLR_EL1 261 orr x1, x1, NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT 262 msr NEOVERSE_N1_CPUECTLR_EL1, x1 2631: 264 ret x17 265endfunc errata_n1_1262888_wa 266 267func check_errata_1262888 268 /* Applies to <=r3p0 */ 269 mov x1, #0x30 270 b cpu_rev_var_ls 271endfunc check_errata_1262888 272 273/* -------------------------------------------------- 274 * Errata Workaround for Neoverse N1 Errata #1275112 275 * This applies to revision <=r3p0 of Neoverse N1. 276 * Inputs: 277 * x0: variant[4:7] and revision[0:3] of current cpu. 278 * Shall clobber: x0-x17 279 * -------------------------------------------------- 280 */ 281func errata_n1_1275112_wa 282 /* Compare x0 against revision r3p0 */ 283 mov x17, x30 284 bl check_errata_1275112 285 cbz x0, 1f 286 mrs x1, NEOVERSE_N1_CPUACTLR_EL1 287 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13 288 msr NEOVERSE_N1_CPUACTLR_EL1, x1 2891: 290 ret x17 291endfunc errata_n1_1275112_wa 292 293func check_errata_1275112 294 /* Applies to <=r3p0 */ 295 mov x1, #0x30 296 b cpu_rev_var_ls 297endfunc check_errata_1275112 298 299/* -------------------------------------------------- 300 * Errata Workaround for Neoverse N1 Erratum 1315703. 301 * This applies to revision <= r3p0 of Neoverse N1. 302 * Inputs: 303 * x0: variant[4:7] and revision[0:3] of current cpu. 304 * Shall clobber: x0-x17 305 * -------------------------------------------------- 306 */ 307func errata_n1_1315703_wa 308 /* Compare x0 against revision r3p1 */ 309 mov x17, x30 310 bl check_errata_1315703 311 cbz x0, 1f 312 313 mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 314 orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 315 msr NEOVERSE_N1_CPUACTLR2_EL1, x0 316 3171: 318 ret x17 319endfunc errata_n1_1315703_wa 320 321func check_errata_1315703 322 /* Applies to everything <= r3p0. */ 323 mov x1, #0x30 324 b cpu_rev_var_ls 325endfunc check_errata_1315703 326 327/* -------------------------------------------------- 328 * Errata Workaround for Neoverse N1 Erratum 1542419. 329 * This applies to revisions r3p0 - r4p0 of Neoverse N1 330 * Inputs: 331 * x0: variant[4:7] and revision[0:3] of current cpu. 332 * Shall clobber: x0-x17 333 * -------------------------------------------------- 334 */ 335func errata_n1_1542419_wa 336 /* Compare x0 against revision r3p0 and r4p0 */ 337 mov x17, x30 338 bl check_errata_1542419 339 cbz x0, 1f 340 341 /* Apply instruction patching sequence */ 342 ldr x0, =0x0 343 msr CPUPSELR_EL3, x0 344 ldr x0, =0xEE670D35 345 msr CPUPOR_EL3, x0 346 ldr x0, =0xFFFF0FFF 347 msr CPUPMR_EL3, x0 348 ldr x0, =0x08000020007D 349 msr CPUPCR_EL3, x0 350 isb 3511: 352 ret x17 353endfunc errata_n1_1542419_wa 354 355func check_errata_1542419 356 /* Applies to everything r3p0 - r4p0. */ 357 mov x1, #0x30 358 mov x2, #0x40 359 b cpu_rev_var_range 360endfunc check_errata_1542419 361 362 /* -------------------------------------------------- 363 * Errata Workaround for Neoverse N1 Errata #1868343. 364 * This applies to revision <= r4p0 of Neoverse N1. 365 * This workaround is the same as the workaround for 366 * errata 1262606 and 1275112 but applies to a wider 367 * revision range. 368 * Inputs: 369 * x0: variant[4:7] and revision[0:3] of current cpu. 370 * Shall clobber: x0-x17 371 * -------------------------------------------------- 372 */ 373func errata_n1_1868343_wa 374 /* 375 * Compare x0 against revision r4p0 376 */ 377 mov x17, x30 378 bl check_errata_1868343 379 cbz x0, 1f 380 mrs x1, NEOVERSE_N1_CPUACTLR_EL1 381 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13 382 msr NEOVERSE_N1_CPUACTLR_EL1, x1 383 isb 3841: 385 ret x17 386endfunc errata_n1_1868343_wa 387 388func check_errata_1868343 389 /* Applies to everything <= r4p0 */ 390 mov x1, #0x40 391 b cpu_rev_var_ls 392endfunc check_errata_1868343 393 394 /* -------------------------------------------------- 395 * Errata Workaround for Neoverse N1 Errata #1946160. 396 * This applies to revisions r3p0, r3p1, r4p0, and 397 * r4p1 of Neoverse N1. It also exists in r0p0, r1p0, 398 * and r2p0 but there is no fix in these revisions. 399 * Inputs: 400 * x0: variant[4:7] and revision[0:3] of current cpu. 401 * Shall clobber: x0-x17 402 * -------------------------------------------------- 403 */ 404func errata_n1_1946160_wa 405 /* 406 * Compare x0 against r3p0 - r4p1 407 */ 408 mov x17, x30 409 bl check_errata_1946160 410 cbz x0, 1f 411 412 mov x0, #3 413 msr S3_6_C15_C8_0, x0 414 ldr x0, =0x10E3900002 415 msr S3_6_C15_C8_2, x0 416 ldr x0, =0x10FFF00083 417 msr S3_6_C15_C8_3, x0 418 ldr x0, =0x2001003FF 419 msr S3_6_C15_C8_1, x0 420 421 mov x0, #4 422 msr S3_6_C15_C8_0, x0 423 ldr x0, =0x10E3800082 424 msr S3_6_C15_C8_2, x0 425 ldr x0, =0x10FFF00083 426 msr S3_6_C15_C8_3, x0 427 ldr x0, =0x2001003FF 428 msr S3_6_C15_C8_1, x0 429 430 mov x0, #5 431 msr S3_6_C15_C8_0, x0 432 ldr x0, =0x10E3800200 433 msr S3_6_C15_C8_2, x0 434 ldr x0, =0x10FFF003E0 435 msr S3_6_C15_C8_3, x0 436 ldr x0, =0x2001003FF 437 msr S3_6_C15_C8_1, x0 438 439 isb 4401: 441 ret x17 442endfunc errata_n1_1946160_wa 443 444func check_errata_1946160 445 /* Applies to r3p0 - r4p1. */ 446 mov x1, #0x30 447 mov x2, #0x41 448 b cpu_rev_var_range 449endfunc check_errata_1946160 450 451 /* ---------------------------------------------------- 452 * Errata Workaround for Neoverse N1 Errata #2743102 453 * This applies to revisions <= r4p1 and is still open. 454 * x0: variant[4:7] and revision[0:3] of current cpu. 455 * Shall clobber: x0-x17 456 * ---------------------------------------------------- 457 */ 458func errata_n1_2743102_wa 459 mov x17, x30 460 bl check_errata_2743102 461 cbz x0, 1f 462 463 /* dsb before isb of power down sequence */ 464 dsb sy 4651: 466 ret x17 467endfunc errata_n1_2743102_wa 468 469func check_errata_2743102 470 /* Applies to all revisions <= r4p1 */ 471 mov x1, #0x41 472 b cpu_rev_var_ls 473endfunc check_errata_2743102 474 475func check_errata_cve_2022_23960 476#if WORKAROUND_CVE_2022_23960 477 mov x0, #ERRATA_APPLIES 478#else 479 mov x0, #ERRATA_MISSING 480#endif 481 ret 482endfunc check_errata_cve_2022_23960 483 484/* -------------------------------------------------- 485 * Disable speculative loads if Neoverse N1 supports 486 * SSBS. 487 * 488 * Shall clobber: x0. 489 * -------------------------------------------------- 490 */ 491func neoverse_n1_disable_speculative_loads 492 /* Check if the PE implements SSBS */ 493 mrs x0, id_aa64pfr1_el1 494 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 495 b.eq 1f 496 497 /* Disable speculative loads */ 498 msr SSBS, xzr 499 5001: 501 ret 502endfunc neoverse_n1_disable_speculative_loads 503 504func neoverse_n1_reset_func 505 mov x19, x30 506 507 bl neoverse_n1_disable_speculative_loads 508 509 /* Forces all cacheable atomic instructions to be near */ 510 mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 511 orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 512 msr NEOVERSE_N1_CPUACTLR2_EL1, x0 513 isb 514 515 bl cpu_get_rev_var 516 mov x18, x0 517 518#if ERRATA_N1_1043202 519 mov x0, x18 520 bl errata_n1_1043202_wa 521#endif 522 523#if ERRATA_N1_1073348 524 mov x0, x18 525 bl errata_n1_1073348_wa 526#endif 527 528#if ERRATA_N1_1130799 529 mov x0, x18 530 bl errata_n1_1130799_wa 531#endif 532 533#if ERRATA_N1_1165347 534 mov x0, x18 535 bl errata_n1_1165347_wa 536#endif 537 538#if ERRATA_N1_1207823 539 mov x0, x18 540 bl errata_n1_1207823_wa 541#endif 542 543#if ERRATA_N1_1220197 544 mov x0, x18 545 bl errata_n1_1220197_wa 546#endif 547 548#if ERRATA_N1_1257314 549 mov x0, x18 550 bl errata_n1_1257314_wa 551#endif 552 553#if ERRATA_N1_1262606 554 mov x0, x18 555 bl errata_n1_1262606_wa 556#endif 557 558#if ERRATA_N1_1262888 559 mov x0, x18 560 bl errata_n1_1262888_wa 561#endif 562 563#if ERRATA_N1_1275112 564 mov x0, x18 565 bl errata_n1_1275112_wa 566#endif 567 568#if ERRATA_N1_1315703 569 mov x0, x18 570 bl errata_n1_1315703_wa 571#endif 572 573#if ERRATA_N1_1542419 574 mov x0, x18 575 bl errata_n1_1542419_wa 576#endif 577 578#if ERRATA_N1_1868343 579 mov x0, x18 580 bl errata_n1_1868343_wa 581#endif 582 583#if ERRATA_N1_1946160 584 mov x0, x18 585 bl errata_n1_1946160_wa 586#endif 587 588#if ENABLE_FEAT_AMU 589 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 590 mrs x0, actlr_el3 591 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT 592 msr actlr_el3, x0 593 594 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 595 mrs x0, actlr_el2 596 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT 597 msr actlr_el2, x0 598 599 /* Enable group0 counters */ 600 mov x0, #NEOVERSE_N1_AMU_GROUP0_MASK 601 msr CPUAMCNTENSET_EL0, x0 602#endif 603 604#if NEOVERSE_Nx_EXTERNAL_LLC 605 /* Some system may have External LLC, core needs to be made aware */ 606 mrs x0, NEOVERSE_N1_CPUECTLR_EL1 607 orr x0, x0, NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT 608 msr NEOVERSE_N1_CPUECTLR_EL1, x0 609#endif 610 611#if ERRATA_DSU_936184 612 bl errata_dsu_936184_wa 613#endif 614 615#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 616 /* 617 * The Neoverse-N1 generic vectors are overridden to apply errata 618 * mitigation on exception entry from lower ELs. 619 */ 620 adr x0, wa_cve_vbar_neoverse_n1 621 msr vbar_el3, x0 622#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ 623 624 isb 625 ret x19 626endfunc neoverse_n1_reset_func 627 628 /* --------------------------------------------- 629 * HW will do the cache maintenance while powering down 630 * --------------------------------------------- 631 */ 632func neoverse_n1_core_pwr_dwn 633 /* --------------------------------------------- 634 * Enable CPU power down bit in power control register 635 * --------------------------------------------- 636 */ 637 mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1 638 orr x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK 639 msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0 640#if ERRATA_N1_2743102 641 mov x15, x30 642 bl cpu_get_rev_var 643 bl errata_n1_2743102_wa 644 mov x30, x15 645#endif /* ERRATA_N1_2743102 */ 646 isb 647 ret 648endfunc neoverse_n1_core_pwr_dwn 649 650#if REPORT_ERRATA 651/* 652 * Errata printing function for Neoverse N1. Must follow AAPCS. 653 */ 654func neoverse_n1_errata_report 655 stp x8, x30, [sp, #-16]! 656 657 bl cpu_get_rev_var 658 mov x8, x0 659 660 /* 661 * Report all errata. The revision-variant information is passed to 662 * checking functions of each errata. 663 */ 664 report_errata ERRATA_N1_1043202, neoverse_n1, 1043202 665 report_errata ERRATA_N1_1073348, neoverse_n1, 1073348 666 report_errata ERRATA_N1_1130799, neoverse_n1, 1130799 667 report_errata ERRATA_N1_1165347, neoverse_n1, 1165347 668 report_errata ERRATA_N1_1207823, neoverse_n1, 1207823 669 report_errata ERRATA_N1_1220197, neoverse_n1, 1220197 670 report_errata ERRATA_N1_1257314, neoverse_n1, 1257314 671 report_errata ERRATA_N1_1262606, neoverse_n1, 1262606 672 report_errata ERRATA_N1_1262888, neoverse_n1, 1262888 673 report_errata ERRATA_N1_1275112, neoverse_n1, 1275112 674 report_errata ERRATA_N1_1315703, neoverse_n1, 1315703 675 report_errata ERRATA_N1_1542419, neoverse_n1, 1542419 676 report_errata ERRATA_N1_1868343, neoverse_n1, 1868343 677 report_errata ERRATA_N1_1946160, neoverse_n1, 1946160 678 report_errata ERRATA_N1_2743102, neoverse_n1, 2743102 679 report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184 680 report_errata WORKAROUND_CVE_2022_23960, neoverse_n1, cve_2022_23960 681 682 ldp x8, x30, [sp], #16 683 ret 684endfunc neoverse_n1_errata_report 685#endif 686 687/* 688 * Handle trap of EL0 IC IVAU instructions to EL3 by executing a TLB 689 * inner-shareable invalidation to an arbitrary address followed by a DSB. 690 * 691 * x1: Exception Syndrome 692 */ 693func neoverse_n1_errata_ic_trap_handler 694 cmp x1, #NEOVERSE_N1_EC_IC_TRAP 695 b.ne 1f 696 tlbi vae3is, xzr 697 dsb sy 698 699 # Skip the IC instruction itself 700 mrs x3, elr_el3 701 add x3, x3, #4 702 msr elr_el3, x3 703 704 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 705 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] 706 ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 707 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 708 709 /* 710 * Issue Error Synchronization Barrier to synchronize SErrors before 711 * exiting EL3. We're running with EAs unmasked, so any synchronized 712 * errors would be taken immediately; therefore no need to inspect 713 * DISR_EL1 register. 714 */ 715 esb 716 exception_return 7171: 718 ret 719endfunc neoverse_n1_errata_ic_trap_handler 720 721 /* --------------------------------------------- 722 * This function provides neoverse_n1 specific 723 * register information for crash reporting. 724 * It needs to return with x6 pointing to 725 * a list of register names in ascii and 726 * x8 - x15 having values of registers to be 727 * reported. 728 * --------------------------------------------- 729 */ 730.section .rodata.neoverse_n1_regs, "aS" 731neoverse_n1_regs: /* The ascii list of register names to be reported */ 732 .asciz "cpuectlr_el1", "" 733 734func neoverse_n1_cpu_reg_dump 735 adr x6, neoverse_n1_regs 736 mrs x8, NEOVERSE_N1_CPUECTLR_EL1 737 ret 738endfunc neoverse_n1_cpu_reg_dump 739 740declare_cpu_ops_eh neoverse_n1, NEOVERSE_N1_MIDR, \ 741 neoverse_n1_reset_func, \ 742 neoverse_n1_errata_ic_trap_handler, \ 743 neoverse_n1_core_pwr_dwn 744