feat(fvp): spmd logical partition smc handler

This patch adds a basic el3 spmd logical partition to the fvp platform
via a platform specific smc handler. One of the use cases for el3
logical partiti

feat(fvp): spmd logical partition smc handler

This patch adds a basic el3 spmd logical partition to the fvp platform
via a platform specific smc handler. One of the use cases for el3
logical partitions is to have the ability to translate sip calls into
ff-a direct requests via the use of spmd logical partitions. The smc
handler creates a direct request based on the incoming smc parameters
and forwards the call as a direct request from the spmd logical
partition to the target secure partition.

Change-Id: If8ba9aab8203924bd00fc1dcdf9cd05a9a04a147

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feat(fvp): add spmd logical partition

This patch changes spmd.mk to include one or more SPMD logical
partitions specific to a platform. It also adds a basic SPMD logical
partition to fvp.

Change-Id

feat(fvp): add spmd logical partition

This patch changes spmd.mk to include one or more SPMD logical
partitions specific to a platform. It also adds a basic SPMD logical
partition to fvp.

Change-Id: I2075e0458c92813913b28cbf4cfffc1f151e65cf
Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>

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feat(spmd): get logical partitions info

This patch enables FF-A secure partitions and the SPMC to query EL3 SPMD
logical partitions that are present in the system via partition get info
regs abi. No

feat(spmd): get logical partitions info

This patch enables FF-A secure partitions and the SPMC to query EL3 SPMD
logical partitions that are present in the system via partition get info
regs abi. Note that normal world will not be able to see EL3 SPMD
logical partitions as per the spec.

Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>
Change-Id: I3fca8aed8ae156a559a74521803324c13ae3d55a

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feat(spmd): add partition info get regs

This patch adds support for an EL3 SPMD logical partition to discover
secure partitions using the FFA_PARTITION_INFO_GET_REGS abi. It also
adds helper functio

feat(spmd): add partition info get regs

This patch adds support for an EL3 SPMD logical partition to discover
secure partitions using the FFA_PARTITION_INFO_GET_REGS abi. It also
adds helper functions for a logical partition to use the information
returned in registers in a meaningful way.

Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>
Change-Id: Id69488e7367e17e2dfa6c8e332be3c8d41f6c773

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refactor(ff-a): move structure definitions

Move ffa_partition_info_get definitions from EL3 SPMC private header
files to common header files. The structures are common to FF-A and are
useful for the

refactor(ff-a): move structure definitions

Move ffa_partition_info_get definitions from EL3 SPMC private header
files to common header files. The structures are common to FF-A and are
useful for the EL3 SPMD logical partitions.

Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>
Change-Id: I19de3f6cb3351afa873022da1397a475a84e3d8b

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feat(spmd): el3 direct message API

This patch implements an API that is exposed to SPMD logical partitions
that can be used to send direct messages to a secure partition.
It also adds required code

feat(spmd): el3 direct message API

This patch implements an API that is exposed to SPMD logical partitions
that can be used to send direct messages to a secure partition.
It also adds required code in the SPMD smc handler to complete the
direct response appropriately.

Change-Id: I2d0e38415f13ad4fd28f8984d565036b7d3a9e71
Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>

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feat(cpus): add support for Gelas CPU

This patch adds the necessary CPU library code to support the Gelas CPU

Change-Id: I13ec4a8bb7055c1ebd0796a4a1378983d930fcb3
Signed-off-by: Juan Pablo Conde <j

feat(cpus): add support for Gelas CPU

This patch adds the necessary CPU library code to support the Gelas CPU

Change-Id: I13ec4a8bb7055c1ebd0796a4a1378983d930fcb3
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

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Merge changes from topic "ar/errata_refactor" into integration

* changes:
refactor(cpus): convert Neoverse Poseidon to use CPU helpers
refactor(cpus): convert Neoverse Poseidon to framework

refactor(cpus): convert Neoverse Poseidon to use CPU helpers

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Icf406c05cdb8d62cd0f41a5f19ae5376707e69bd

refactor(cpus): convert Neoverse Poseidon to framework

This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_re

refactor(cpus): convert Neoverse Poseidon to framework

This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically
...and for each erratum:
* the prologue with the workaround_<type>_start to do the checks and
framework registration automatically
* the epilogue with the workaround_<type>_end
* the checker function with the check_erratum_<type> to make it more
descriptive

It is important to note that the errata workaround sequences remain
unchanged and preserve their git blame.

Testing was conducted by:

* Manual comparison of disassembly of converted functions with non-
converted functions

aarch64-none-elf-objdump -D <trusted-firmware-a with conversion>/build/fvp/release/bl31/bl31.elf
vs
aarch64-none-elf-objdump -D <trusted-firmware-a clean repo>/build/fvp/release/bl31/bl31.elf

* Build for release with all errata flags enabled and run default tftf
tests

CROSS_COMPILE=aarch64-none-elf- make PLAT=fvp DEBUG=0 \
CTX_INCLUDE_AARCH32_REGS=0 HW_ASSISTED_COHERENCY=1 USE_COHERENT_MEM=0 \
BL33=./../tf-a-tests/build/fvp/release/tftf.bin \
WORKAROUND_CVE_2022_23960=1 ERRATA_ABI_SUPPORT=1 all fip

* Build for debug with all errata enabled and step through ArmDS
at reset to ensure all functions are entered.

Change-Id: I34e27e468d4f971423a03a95a4a52f4af8bd783a
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>

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Merge "fix: .gitignore to include memory tools" into integration

Merge changes from topic "ar/errata_refactor" into integration

* changes:
refactor(cpus): convert Neoverse V2 to use CPU helpers
refactor(cpus): convert Neoverse V2 to framework

Merge changes I2f4961fe,I0039c724,Iaa3076c1,Ic19973a8 into integration

* changes:
feat(bl32): print entry point before exiting SP_MIN
fix(bl32): avoid clearing argument registers in RESET_TO_SP_

Merge changes I2f4961fe,I0039c724,Iaa3076c1,Ic19973a8 into integration

* changes:
feat(bl32): print entry point before exiting SP_MIN
fix(bl32): avoid clearing argument registers in RESET_TO_SP_MIN case
fix(bl32): always include arm_arch_svc in SP_MIN
fix(services): disable workaround discovery on aarch32 for now

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fix: .gitignore to include memory tools

Added to .gitignore the following path, as it was
noticed as untracked after a TF-A CI run:
tools/memory/memory/__pycache__/

Signed-off-by: J-Alves <joao.alv

fix: .gitignore to include memory tools

Added to .gitignore the following path, as it was
noticed as untracked after a TF-A CI run:
tools/memory/memory/__pycache__/

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I35ba6f6a33593671c11f8e33c28545ae9bc57b4c

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feat(sptool): generate `ARM_BL2_SP_LIST_DTS` file from `sp_layout.json`

TF-A makefile accepts a device-tree snippet to override hardcoded SP
nodes, via the `ARM_BL2_SP_LIST_DTS` variable. However th

feat(sptool): generate `ARM_BL2_SP_LIST_DTS` file from `sp_layout.json`

TF-A makefile accepts a device-tree snippet to override hardcoded SP
nodes, via the `ARM_BL2_SP_LIST_DTS` variable. However the SPs declared
in `ARM_BL2_SP_LIST_DTS` must be in the same order as they are in the
FIP image, otherwise hash authentication will fail when loaded by BL2.

This patch generates the `ARM_BL2_SP_LIST_DTS` file from the
`sp_layout.json` file. The SPs in the FIP image are also generated from
`sp_layout.json`, so this ensures that there is only one source of truth
for the SP list, removing the possibility to have the lists disagree
with each other.

Signed-off-by: Karl Meakin <karl.meakin@arm.com>
Change-Id: I7d76715135c596605c6a02aad5196d967dfeb1ce

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refactor(cpus): convert Neoverse V2 to use CPU helpers

Convert Neoverse V2 to use CPU helpers, in this case that's
only two spots.

Change-Id: Icd250f92974e8a50c459038de7644a2e68007589
Signed-off-by

refactor(cpus): convert Neoverse V2 to use CPU helpers

Convert Neoverse V2 to use CPU helpers, in this case that's
only two spots.

Change-Id: Icd250f92974e8a50c459038de7644a2e68007589
Signed-off-by: Moritz Fischer <moritzf@google.com>
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>

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refactor(cpus): convert Neoverse V2 to framework

For V2, this involves replacing:
- The reset_func with the standard cpu_reset_func_{start,end}
to apply errata automatically
- The <cpu>_erra

refactor(cpus): convert Neoverse V2 to framework

For V2, this involves replacing:
- The reset_func with the standard cpu_reset_func_{start,end}
to apply errata automatically
- The <cpu>_errata_report with the errata_report_shim to
report errata automatically

And for each erratum:
- The prologue with the workaround_<type>_start to do the checks and
framework registration automatically at reset or runtime
- The epilogue with the workaround_<type>_end
- The checker function with the check_erratum_<type> to check whether
the erratum applies on the revision of the CPU.

It is important to note that the errata workaround sequences remain
unchanged and preserve their git blame.

Testing was conducted by:

* Manual comparison of disassembly of converted functions with non-
converted functions

aarch64-none-elf-objdump -D <trusted-firmware-a with conversion>/build/fvp/release/bl31/bl31.elf
vs
aarch64-none-elf-objdump -D <trusted-firmware-a clean repo>/build/fvp/release/bl31/bl31.elf

* Build for release with all errata flags enabled and run default tftf
tests

CROSS_COMPILE=aarch64-none-elf- make PLAT=fvp CTX_INCLUDE_AARCH32_REGS=0 \
HW_ASSISTED_COHERENCY=1 USE_COHERENT_MEM=0 \
BL33=./../tf-a-tests/build/fvp/debug/tftf.bin \
ERRATA_V2_2801372 WORKAROUND_CVE_2022_23960=1 ERRATA_ABI_SUPPORT=1 all fip

* Build for debug with all errata enabled and step through ArmDS
at reset to ensure all functions are entered.

Change-Id: Ic968844d6aabea3867189d747769ced8faa87e56
Signed-off-by: Moritz Fischer <moritzf@google.com>
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>

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Merge "fix(cpus): assert invalid cpu_ops obtained" into integration

Merge "docs: add instructions for PDF generation of docs" into integration

fix(cpus): assert invalid cpu_ops obtained

Not including the proper CPU file can halt execution at the
reset_handler since the cpu_ops obtained will be invalid and therefore
the cpu reset function w

fix(cpus): assert invalid cpu_ops obtained

Not including the proper CPU file can halt execution at the
reset_handler since the cpu_ops obtained will be invalid and therefore
the cpu reset function will be invalid too, unless SUPPORT_UNKNOWN_MPID
is enabled.

This patch adds an assert to check for the validity of the obtained
cpu_ops object and will display an error if the object is invalid.

Change-Id: I0e1661745e4a692aab5e910e110c2de0caf64f46
Signed-off-by: Thaddeus Serna <Thaddeus.Gonzalez-Serna@arm.com>

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Merge changes from topic "xlnx_security_flag_change" into integration

* changes:
fix(versal-net): make pmc ipi channel as secure
fix(versal): make pmc ipi channel as secure
fix(versal-net): ad

Merge changes from topic "xlnx_security_flag_change" into integration

* changes:
fix(versal-net): make pmc ipi channel as secure
fix(versal): make pmc ipi channel as secure
fix(versal-net): add redundant call to avoid glitches
fix(versal-net): change flag to increase security

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Merge "fix(cpus): flush L2 cache for Cortex-A7/12/15/17" into integration

docs: add instructions for PDF generation of docs

This patch details the required packages and terminal commands for
building the documentation in PDF format locally.

Change-Id: Ic5f416b73e46d5f362

docs: add instructions for PDF generation of docs

This patch details the required packages and terminal commands for
building the documentation in PDF format locally.

Change-Id: Ic5f416b73e46d5f362fe9eb909200b95eda19e6a
Signed-off-by: Elizabeth Ho <elizabeth.ho@arm.com>

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fix(cpus): flush L2 cache for Cortex-A7/12/15/17

Similar to Cortex-A53, the AArch32-only Cortex-A7/12/15/17 have an
(optional) integrated L2 cache that might need to be flushed if the
whole cluster

fix(cpus): flush L2 cache for Cortex-A7/12/15/17

Similar to Cortex-A53, the AArch32-only Cortex-A7/12/15/17 have an
(optional) integrated L2 cache that might need to be flushed if the
whole cluster is powered down. However, unlike Cortex-A53 there is
currently no L2 cache flush in the cluster_pwr_dwn implementation for
some reason. This causes problems if there is unwritten data left in
the L2 cache during a cluster power off.

Fix this by adding the L2 cache flush similar to cortex_a53.S.

Change-Id: Icd087bef9acff11e03edcaa0d26dd8b8e30796b7
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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Merge "docs: remove blank pages from PDF documentation" into integration