1Arm CPU Specific Build Macros 2============================= 3 4This document describes the various build options present in the CPU specific 5operations framework to enable errata workarounds and to enable optimizations 6for a specific CPU on a platform. 7 8Security Vulnerability Workarounds 9---------------------------------- 10 11TF-A exports a series of build flags which control which security 12vulnerability workarounds should be applied at runtime. 13 14- ``WORKAROUND_CVE_2017_5715``: Enables the security workaround for 15 `CVE-2017-5715`_. This flag can be set to 0 by the platform if none 16 of the PEs in the system need the workaround. Setting this flag to 0 provides 17 no performance benefit for non-affected platforms, it just helps to comply 18 with the recommendation in the spec regarding workaround discovery. 19 Defaults to 1. 20 21- ``WORKAROUND_CVE_2018_3639``: Enables the security workaround for 22 `CVE-2018-3639`_. Defaults to 1. The TF-A project recommends to keep 23 the default value of 1 even on platforms that are unaffected by 24 CVE-2018-3639, in order to comply with the recommendation in the spec 25 regarding workaround discovery. 26 27- ``DYNAMIC_WORKAROUND_CVE_2018_3639``: Enables dynamic mitigation for 28 `CVE-2018-3639`_. This build option should be set to 1 if the target 29 platform contains at least 1 CPU that requires dynamic mitigation. 30 Defaults to 0. 31 32- ``WORKAROUND_CVE_2022_23960``: Enables mitigation for `CVE-2022-23960`_. 33 This build option should be set to 1 if the target platform contains at 34 least 1 CPU that requires this mitigation. Defaults to 1. 35 36.. _arm_cpu_macros_errata_workarounds: 37 38CPU Errata Workarounds 39---------------------- 40 41TF-A exports a series of build flags which control the errata workarounds that 42are applied to each CPU by the reset handler. The errata details can be found 43in the CPU specific errata documents published by Arm: 44 45- `Cortex-A53 MPCore Software Developers Errata Notice`_ 46- `Cortex-A57 MPCore Software Developers Errata Notice`_ 47- `Cortex-A72 MPCore Software Developers Errata Notice`_ 48 49The errata workarounds are implemented for a particular revision or a set of 50processor revisions. This is checked by the reset handler at runtime. Each 51errata workaround is identified by its ``ID`` as specified in the processor's 52errata notice document. The format of the define used to enable/disable the 53errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name`` 54is for example ``A57`` for the ``Cortex_A57`` CPU. 55 56Refer to :ref:`firmware_design_cpu_errata_implementation` for information on how to 57write errata workaround functions. 58 59All workarounds are disabled by default. The platform is responsible for 60enabling these workarounds according to its requirement by defining the 61errata workaround build flags in the platform specific makefile. In case 62these workarounds are enabled for the wrong CPU revision then the errata 63workaround is not applied. In the DEBUG build, this is indicated by 64printing a warning to the crash console. 65 66In the current implementation, a platform which has more than 1 variant 67with different revisions of a processor has no runtime mechanism available 68for it to specify which errata workarounds should be enabled or not. 69 70The value of the build flags is 0 by default, that is, disabled. A value of 1 71will enable it. 72 73For Cortex-A9, the following errata build flags are defined : 74 75- ``ERRATA_A9_794073``: This applies errata 794073 workaround to Cortex-A9 76 CPU. This needs to be enabled for all revisions of the CPU. 77 78For Cortex-A15, the following errata build flags are defined : 79 80- ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15 81 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. 82 83- ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15 84 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. 85 86For Cortex-A17, the following errata build flags are defined : 87 88- ``ERRATA_A17_852421``: This applies errata 852421 workaround to Cortex-A17 89 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 90 91- ``ERRATA_A17_852423``: This applies errata 852423 workaround to Cortex-A17 92 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 93 94For Cortex-A35, the following errata build flags are defined : 95 96- ``ERRATA_A35_855472``: This applies errata 855472 workaround to Cortex-A35 97 CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35. 98 99For Cortex-A53, the following errata build flags are defined : 100 101- ``ERRATA_A53_819472``: This applies errata 819472 workaround to all 102 CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53. 103 104- ``ERRATA_A53_824069``: This applies errata 824069 workaround to all 105 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. 106 107- ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53 108 CPU. This needs to be enabled only for revision <= r0p2 of the CPU. 109 110- ``ERRATA_A53_827319``: This applies errata 827319 workaround to all 111 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. 112 113- ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and 114 link time to Cortex-A53 CPU. This needs to be enabled for some variants of 115 revision <= r0p4. This workaround can lead the linker to create ``*.stub`` 116 sections. 117 118- ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53 119 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From 120 r0p4 and onwards, this errata is enabled by default in hardware. Identical to 121 ``A53_DISABLE_NON_TEMPORAL_HINT``. 122 123- ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time 124 to Cortex-A53 CPU. This needs to be enabled for some variants of revision 125 <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections 126 which are 4kB aligned. 127 128- ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53 129 CPUs. Though the erratum is present in every revision of the CPU, 130 this workaround is only applied to CPUs from r0p3 onwards, which feature 131 a chicken bit in CPUACTLR_EL1 to enable a hardware workaround. 132 Earlier revisions of the CPU have other errata which require the same 133 workaround in software, so they should be covered anyway. 134 135- ``ERRATA_A53_1530924``: This applies errata 1530924 workaround to all 136 revisions of Cortex-A53 CPU. 137 138For Cortex-A55, the following errata build flags are defined : 139 140- ``ERRATA_A55_768277``: This applies errata 768277 workaround to Cortex-A55 141 CPU. This needs to be enabled only for revision r0p0 of the CPU. 142 143- ``ERRATA_A55_778703``: This applies errata 778703 workaround to Cortex-A55 144 CPU. This needs to be enabled only for revision r0p0 of the CPU. 145 146- ``ERRATA_A55_798797``: This applies errata 798797 workaround to Cortex-A55 147 CPU. This needs to be enabled only for revision r0p0 of the CPU. 148 149- ``ERRATA_A55_846532``: This applies errata 846532 workaround to Cortex-A55 150 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 151 152- ``ERRATA_A55_903758``: This applies errata 903758 workaround to Cortex-A55 153 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 154 155- ``ERRATA_A55_1221012``: This applies errata 1221012 workaround to Cortex-A55 156 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 157 158- ``ERRATA_A55_1530923``: This applies errata 1530923 workaround to all 159 revisions of Cortex-A55 CPU. 160 161For Cortex-A57, the following errata build flags are defined : 162 163- ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57 164 CPU. This needs to be enabled only for revision r0p0 of the CPU. 165 166- ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57 167 CPU. This needs to be enabled only for revision r0p0 of the CPU. 168 169- ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57 170 CPU. This needs to be enabled only for revision r0p0 of the CPU. 171 172- ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57 173 CPU. This needs to be enabled only for revision r0p0 of the CPU. 174 175- ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57 176 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 177 178- ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57 179 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 180 181- ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57 182 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 183 184- ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57 185 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 186 187- ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57 188 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 189 190- ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57 191 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 192 193- ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57 194 CPU. This needs to be enabled only for revision <= r1p3 of the CPU. 195 196- ``ERRATA_A57_1319537``: This applies errata 1319537 workaround to all 197 revisions of Cortex-A57 CPU. 198 199For Cortex-A72, the following errata build flags are defined : 200 201- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72 202 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. 203 204- ``ERRATA_A72_1319367``: This applies errata 1319367 workaround to all 205 revisions of Cortex-A72 CPU. 206 207For Cortex-A73, the following errata build flags are defined : 208 209- ``ERRATA_A73_852427``: This applies errata 852427 workaround to Cortex-A73 210 CPU. This needs to be enabled only for revision r0p0 of the CPU. 211 212- ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73 213 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 214 215For Cortex-A75, the following errata build flags are defined : 216 217- ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75 218 CPU. This needs to be enabled only for revision r0p0 of the CPU. 219 220- ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75 221 CPU. This needs to be enabled only for revision r0p0 of the CPU. 222 223For Cortex-A76, the following errata build flags are defined : 224 225- ``ERRATA_A76_1073348``: This applies errata 1073348 workaround to Cortex-A76 226 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 227 228- ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76 229 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 230 231- ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76 232 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 233 234- ``ERRATA_A76_1257314``: This applies errata 1257314 workaround to Cortex-A76 235 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 236 237- ``ERRATA_A76_1262606``: This applies errata 1262606 workaround to Cortex-A76 238 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 239 240- ``ERRATA_A76_1262888``: This applies errata 1262888 workaround to Cortex-A76 241 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 242 243- ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76 244 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 245 246- ``ERRATA_A76_1791580``: This applies errata 1791580 workaround to Cortex-A76 247 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 248 249- ``ERRATA_A76_1165522``: This applies errata 1165522 workaround to all 250 revisions of Cortex-A76 CPU. This errata is fixed in r3p0 but due to 251 limitation of errata framework this errata is applied to all revisions 252 of Cortex-A76 CPU. 253 254- ``ERRATA_A76_1868343``: This applies errata 1868343 workaround to Cortex-A76 255 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 256 257- ``ERRATA_A76_1946160``: This applies errata 1946160 workaround to Cortex-A76 258 CPU. This needs to be enabled only for revisions r3p0 - r4p1 of the CPU. 259 260- ``ERRATA_A76_2743102``: This applies errata 2743102 workaround to Cortex-A76 261 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is 262 still open. 263 264For Cortex-A77, the following errata build flags are defined : 265 266- ``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77 267 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 268 269- ``ERRATA_A77_1925769``: This applies errata 1925769 workaround to Cortex-A77 270 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 271 272- ``ERRATA_A77_1946167``: This applies errata 1946167 workaround to Cortex-A77 273 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 274 275- ``ERRATA_A77_1791578``: This applies errata 1791578 workaround to Cortex-A77 276 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 277 278- ``ERRATA_A77_2356587``: This applies errata 2356587 workaround to Cortex-A77 279 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 280 281 - ``ERRATA_A77_1800714``: This applies errata 1800714 workaround to Cortex-A77 282 CPU. This needs to be enabled for revisions <= r1p1 of the CPU. 283 284 - ``ERRATA_A77_2743100``: This applies errata 2743100 workaround to Cortex-A77 285 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 286 287For Cortex-A78, the following errata build flags are defined : 288 289- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78 290 CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU. 291 292- ``ERRATA_A78_1941498``: This applies errata 1941498 workaround to Cortex-A78 293 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. 294 295- ``ERRATA_A78_1951500``: This applies errata 1951500 workaround to Cortex-A78 296 CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same 297 issue but there is no workaround for that revision. 298 299- ``ERRATA_A78_1821534``: This applies errata 1821534 workaround to Cortex-A78 300 CPU. This needs to be enabled for revisions r0p0 and r1p0. 301 302- ``ERRATA_A78_1952683``: This applies errata 1952683 workaround to Cortex-A78 303 CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0. 304 305- ``ERRATA_A78_2132060``: This applies errata 2132060 workaround to Cortex-A78 306 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2. It 307 is still open. 308 309- ``ERRATA_A78_2242635``: This applies errata 2242635 workaround to Cortex-A78 310 CPU. This needs to be enabled for revisions r1p0, r1p1, and r1p2. The issue 311 is present in r0p0 but there is no workaround. It is still open. 312 313- ``ERRATA_A78_2376745``: This applies errata 2376745 workaround to Cortex-A78 314 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 315 it is still open. 316 317- ``ERRATA_A78_2395406``: This applies errata 2395406 workaround to Cortex-A78 318 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 319 it is still open. 320 321- ``ERRATA_A78_2712571``: This applies erratum 2712571 workaround to Cortex-A78 322 CPU, this erratum affects system configurations that do not use an ARM 323 interconnect IP. This needs to be enabled for revisions r0p0, r1p0, r1p1 324 and r1p2 and it is still open. 325 326- ``ERRATA_A78_2742426``: This applies erratum 2742426 workaround to Cortex-A78 327 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and 328 it is still open. 329 330- ``ERRATA_A78_2772019``: This applies errata 2772019 workaround to Cortex-A78 331 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 332 it is still open. 333 334- ``ERRATA_A78_2779479``: This applies erratum 2779479 workaround to Cortex-A78 335 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and 336 it is still open. 337 338For Cortex-A78 AE, the following errata build flags are defined : 339 340- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to 341 Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. 342 This erratum is still open. 343 344- ``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to 345 Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This 346 erratum is still open. 347 348- ``ERRATA_A78_AE_2376748`` : This applies errata 2376748 workaround to 349 Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This 350 erratum is still open. 351 352- ``ERRATA_A78_AE_2395408`` : This applies errata 2395408 workaround to 353 Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This 354 erratum is still open. 355 356- ``ERRATA_A78_AE_2712574`` : This applies erratum 2712574 workaround to 357 Cortex-A78 AE CPU. This erratum affects system configurations that do not use 358 an ARM interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and 359 r0p2. This erratum is still open. 360 361For Cortex-A78C, the following errata build flags are defined : 362 363- ``ERRATA_A78C_1827430`` : This applies errata 1827430 workaround to 364 Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is 365 fixed in r0p1. 366 367- ``ERRATA_A78C_1827440`` : This applies errata 1827440 workaround to 368 Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is 369 fixed in r0p1. 370 371- ``ERRATA_A78C_2132064`` : This applies errata 2132064 workaround to 372 Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and 373 it is still open. 374 375- ``ERRATA_A78C_2242638`` : This applies errata 2242638 workaround to 376 Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and 377 it is still open. 378 379- ``ERRATA_A78C_2376749`` : This applies errata 2376749 workaround to 380 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 381 erratum is still open. 382 383- ``ERRATA_A78C_2395411`` : This applies errata 2395411 workaround to 384 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 385 erratum is still open. 386 387- ``ERRATA_A78C_2712575`` : This applies erratum 2712575 workaround to 388 Cortex-A78C CPU, this erratum affects system configurations that do not use 389 an ARM interconnect IP. This needs to be enabled for revisions r0p1 and r0p2 390 and is still open. 391 392- ``ERRATA_A78C_2772121`` : This applies errata 2772121 workaround to 393 Cortex-A78C CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 394 This erratum is still open. 395 396- ``ERRATA_A78C_2779484`` : This applies errata 2779484 workaround to 397 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. 398 This erratum is still open. 399 400For Cortex-X1 CPU, the following errata build flags are defined: 401 402- ``ERRATA_X1_1821534`` : This applies errata 1821534 workaround to Cortex-X1 403 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 404 405- ``ERRATA_X1_1688305`` : This applies errata 1688305 workaround to Cortex-X1 406 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 407 408- ``ERRATA_X1_1827429`` : This applies errata 1827429 workaround to Cortex-X1 409 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 410 411For Neoverse N1, the following errata build flags are defined : 412 413- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1 414 CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU. 415 416- ``ERRATA_N1_1130799``: This applies errata 1130799 workaround to Neoverse-N1 417 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 418 419- ``ERRATA_N1_1165347``: This applies errata 1165347 workaround to Neoverse-N1 420 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 421 422- ``ERRATA_N1_1207823``: This applies errata 1207823 workaround to Neoverse-N1 423 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 424 425- ``ERRATA_N1_1220197``: This applies errata 1220197 workaround to Neoverse-N1 426 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 427 428- ``ERRATA_N1_1257314``: This applies errata 1257314 workaround to Neoverse-N1 429 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 430 431- ``ERRATA_N1_1262606``: This applies errata 1262606 workaround to Neoverse-N1 432 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 433 434- ``ERRATA_N1_1262888``: This applies errata 1262888 workaround to Neoverse-N1 435 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 436 437- ``ERRATA_N1_1275112``: This applies errata 1275112 workaround to Neoverse-N1 438 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 439 440- ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1 441 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 442 443- ``ERRATA_N1_1542419``: This applies errata 1542419 workaround to Neoverse-N1 444 CPU. This needs to be enabled only for revisions r3p0 - r4p0 of the CPU. 445 446- ``ERRATA_N1_1868343``: This applies errata 1868343 workaround to Neoverse-N1 447 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 448 449- ``ERRATA_N1_1946160``: This applies errata 1946160 workaround to Neoverse-N1 450 CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for 451 revisions r0p0, r1p0, and r2p0 there is no workaround. 452 453- ``ERRATA_N1_2743102``: This applies errata 2743102 workaround to Neoverse-N1 454 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is 455 still open. 456 457For Neoverse V1, the following errata build flags are defined : 458 459- ``ERRATA_V1_1618635``: This applies errata 1618635 workaround to Neoverse-V1 460 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 461 r1p0. 462 463- ``ERRATA_V1_1774420``: This applies errata 1774420 workaround to Neoverse-V1 464 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 465 in r1p1. 466 467- ``ERRATA_V1_1791573``: This applies errata 1791573 workaround to Neoverse-V1 468 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 469 in r1p1. 470 471- ``ERRATA_V1_1852267``: This applies errata 1852267 workaround to Neoverse-V1 472 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 473 in r1p1. 474 475- ``ERRATA_V1_1925756``: This applies errata 1925756 workaround to Neoverse-V1 476 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 477 478- ``ERRATA_V1_1940577``: This applies errata 1940577 workaround to Neoverse-V1 479 CPU. This needs to be enabled only for revision r1p0 and r1p1 of the 480 CPU. 481 482- ``ERRATA_V1_1966096``: This applies errata 1966096 workaround to Neoverse-V1 483 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the 484 issue is present in r0p0 as well but there is no workaround for that 485 revision. It is still open. 486 487- ``ERRATA_V1_2139242``: This applies errata 2139242 workaround to Neoverse-V1 488 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the 489 CPU. It is still open. 490 491- ``ERRATA_V1_2108267``: This applies errata 2108267 workaround to Neoverse-V1 492 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. 493 It is still open. 494 495- ``ERRATA_V1_2216392``: This applies errata 2216392 workaround to Neoverse-V1 496 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the 497 issue is present in r0p0 as well but there is no workaround for that 498 revision. It is still open. 499 500- ``ERRATA_V1_2294912``: This applies errata 2294912 workaround to Neoverse-V1 501 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. 502 503- ``ERRATA_V1_2372203``: This applies errata 2372203 workaround to Neoverse-V1 504 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU. 505 It is still open. 506 507- ``ERRATA_V1_2701953``: This applies erratum 2701953 workaround to Neoverse-V1 508 CPU, this erratum affects system configurations that do not use an ARM 509 interconnect IP. This needs to be enabled for revisions r0p0, r1p0 and r1p1. 510 It has been fixed in r1p2. 511 512- ``ERRATA_V1_2743093``: This applies errata 2743093 workaround to Neoverse-V1 513 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 of the 514 CPU. It is still open. 515 516- ``ERRATA_V1_2743233``: This applies erratum 2743233 workaround to Neoverse-V1 517 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2 of the 518 CPU. It is still open. 519 520- ``ERRATA_V1_2779461``: This applies erratum 2779461 workaround to Neoverse-V1 521 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, r1p2 of the 522 CPU. It is still open. 523 524For Neoverse V2, the following errata build flags are defined : 525 526- ``ERRATA_V2_2331132``: This applies errata 2331132 workaround to Neoverse-V2 527 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is still 528 open. 529 530- ``ERRATA_V2_2719103``: This applies errata 2719103 workaround to Neoverse-V2 531 CPU, this affects system configurations that do not use and ARM interconnect 532 IP. This needs to be enabled for revisions r0p0 and r0p1. It has been fixed 533 in r0p2. 534 535- ``ERRATA_V2_2719105``: This applies errata 2719105 workaround to Neoverse-V2 536 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 537 r0p2. 538 539- ``ERRATA_V2_2743011``: This applies errata 2743011 workaround to Neoverse-V2 540 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 541 r0p2. 542 543- ``ERRATA_V2_2779510``: This applies errata 2779510 workaround to Neoverse-V2 544 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 545 r0p2. 546 547- ``ERRATA_V2_2801372``: This applies errata 2801372 workaround to Neoverse-V2 548 CPU, this affects all configurations. This needs to be enabled for revisions 549 r0p0 and r0p1. It has been fixed in r0p2. 550 551For Cortex-A710, the following errata build flags are defined : 552 553- ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to 554 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 555 r2p0 of the CPU. It is still open. 556 557- ``ERRATA_A710_2081180``: This applies errata 2081180 workaround to 558 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 559 r2p0 of the CPU. It is still open. 560 561- ``ERRATA_A710_2055002``: This applies errata 2055002 workaround to 562 Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU 563 and is still open. 564 565- ``ERRATA_A710_2017096``: This applies errata 2017096 workaround to 566 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 567 of the CPU and is still open. 568 569- ``ERRATA_A710_2083908``: This applies errata 2083908 workaround to 570 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU and 571 is still open. 572 573- ``ERRATA_A710_2058056``: This applies errata 2058056 workaround to 574 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 575 of the CPU and is still open. 576 577- ``ERRATA_A710_2267065``: This applies errata 2267065 workaround to 578 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 579 of the CPU and is fixed in r2p1. 580 581- ``ERRATA_A710_2136059``: This applies errata 2136059 workaround to 582 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 583 of the CPU and is fixed in r2p1. 584 585- ``ERRATA_A710_2147715``: This applies errata 2147715 workaround to 586 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU 587 and is fixed in r2p1. 588 589- ``ERRATA_A710_2216384``: This applies errata 2216384 workaround to 590 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 591 of the CPU and is fixed in r2p1. 592 593- ``ERRATA_A710_2282622``: This applies errata 2282622 workaround to 594 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 595 r2p1 of the CPU and is still open. 596 597- ``ERRATA_A710_2291219``: This applies errata 2291219 workaround to 598 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 599 of the CPU and is fixed in r2p1. 600 601- ``ERRATA_A710_2008768``: This applies errata 2008768 workaround to 602 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 603 of the CPU and is fixed in r2p1. 604 605- ``ERRATA_A710_2371105``: This applies errata 2371105 workaround to 606 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 607 of the CPU and is fixed in r2p1. 608 609- ``ERRATA_A710_2701952``: This applies erratum 2701952 workaround to Cortex-A710 610 CPU, and applies to system configurations that do not use and ARM 611 interconnect IP. This needs to be enabled for r0p0, r1p0, r2p0 and r2p1 and 612 is still open. 613 614- ``ERRATA_A710_2768515``: This applies errata 2768515 workaround to 615 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 616 r2p1 of the CPU and is still open. 617 618For Neoverse N2, the following errata build flags are defined : 619 620- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2 621 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 622 623- ``ERRATA_N2_2009478``: This applies errata 2009478 workaround to Neoverse-N2 624 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 625 626- ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2 627 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 628 629- ``ERRATA_N2_2025414``: This applies errata 2025414 workaround to Neoverse-N2 630 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 631 632- ``ERRATA_N2_2189731``: This applies errata 2189731 workaround to Neoverse-N2 633 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 634 635- ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2 636 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 637 638- ``ERRATA_N2_2138953``: This applies errata 2138953 workaround to Neoverse-N2 639 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is still open. 640 641- ``ERRATA_N2_2242415``: This applies errata 2242415 workaround to Neoverse-N2 642 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 643 644- ``ERRATA_N2_2138958``: This applies errata 2138958 workaround to Neoverse-N2 645 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 646 647- ``ERRATA_N2_2242400``: This applies errata 2242400 workaround to Neoverse-N2 648 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 649 650- ``ERRATA_N2_2280757``: This applies errata 2280757 workaround to Neoverse-N2 651 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 652 653- ``ERRATA_N2_2326639``: This applies errata 2326639 workaround to Neoverse-N2 654 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 655 r0p1. 656 657- ``ERRATA_N2_2376738``: This applies errata 2376738 workaround to Neoverse-N2 658 CPU. This needs to be enabled for revision r0p0, r0p1, r0p2, r0p3 and is still open. 659 660- ``ERRATA_N2_2388450``: This applies errata 2388450 workaround to Neoverse-N2 661 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 662 r0p1. 663 664- ``ERRATA_N2_2743014``: This applies errata 2743014 workaround to Neoverse-N2 665 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 666 in r0p3. 667 668- ``ERRATA_N2_2743089``: This applies errata 2743089 workaround to Neoverse-N2 669 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 670 in r0p3. 671 672- ``ERRATA_N2_2728475``: This applies erratum 2728475 workaround to Neoverse-N2 673 CPU, this erratum affects system configurations that do not use and ARM 674 interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 675 It is fixed in r0p3. 676 677- ``ERRATA_N2_2779511``: This applies errata 2779511 workaround to Neoverse-N2 678 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 679 in r0p3. 680 681For Cortex-X2, the following errata build flags are defined : 682 683- ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2 684 CPU. This needs to be enabled for revisions r0p0, r1p0, and r2p0 of the CPU, 685 it is still open. 686 687- ``ERRATA_X2_2058056``: This applies errata 2058056 workaround to Cortex-X2 688 CPU. This needs to be enabled for revisions r0p0, r1p0, and r2p0 of the CPU, 689 it is still open. 690 691- ``ERRATA_X2_2083908``: This applies errata 2083908 workaround to Cortex-X2 692 CPU. This needs to be enabled for revision r2p0 of the CPU, it is still open. 693 694- ``ERRATA_X2_2017096``: This applies errata 2017096 workaround to Cortex-X2 695 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 696 CPU, it is fixed in r2p1. 697 698- ``ERRATA_X2_2081180``: This applies errata 2081180 workaround to Cortex-X2 699 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 700 CPU, it is fixed in r2p1. 701 702- ``ERRATA_X2_2216384``: This applies errata 2216384 workaround to Cortex-X2 703 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 704 CPU, it is fixed in r2p1. 705 706- ``ERRATA_X2_2147715``: This applies errata 2147715 workaround to Cortex-X2 707 CPU. This needs to be enabled only for revision r2p0 of the CPU, it is fixed 708 in r2p1. 709 710- ``ERRATA_X2_2282622``: This applies errata 2282622 workaround to Cortex-X2 711 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 712 CPU and is still open. 713 714- ``ERRATA_X2_2371105``: This applies errata 2371105 workaround to Cortex-X2 715 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 of the CPU 716 and is fixed in r2p1. 717 718- ``ERRATA_X2_2701952``: This applies erratum 2701952 workaround to Cortex-X2 719 CPU and affects system configurations that do not use an ARM interconnect IP. 720 This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 and is 721 still open. 722 723- ``ERRATA_X2_2768515``: This applies errata 2768515 workaround to Cortex-X2 724 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 725 CPU and is still open. 726 727For Cortex-X3, the following errata build flags are defined : 728 729- ``ERRATA_X3_2070301``: This applies errata 2070301 workaround to the Cortex-X3 730 CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2 of 731 the CPU and is still open. 732 733- ``ERRATA_X3_2313909``: This applies errata 2313909 workaround to 734 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0 735 of the CPU, it is fixed in r1p1. 736 737- ``ERRATA_X3_2615812``: This applies errata 2615812 workaround to Cortex-X3 738 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the 739 CPU, it is still open. 740 741- ``ERRATA_X3_2742421``: This applies errata 2742421 workaround to 742 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 743 r1p1. It is fixed in r1p2. 744 745For Cortex-A510, the following errata build flags are defined : 746 747- ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to 748 Cortex-A510 CPU. This needs to be enabled only for revision r0p0, it is 749 fixed in r0p1. 750 751- ``ERRATA_A510_2288014``: This applies errata 2288014 workaround to 752 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1, 753 r0p2, r0p3 and r1p0, it is fixed in r1p1. 754 755- ``ERRATA_A510_2042739``: This applies errata 2042739 workaround to 756 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1 and 757 r0p2, it is fixed in r0p3. 758 759- ``ERRATA_A510_2041909``: This applies errata 2041909 workaround to 760 Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is fixed 761 in r0p3. The issue is also present in r0p0 and r0p1 but there is no 762 workaround for those revisions. 763 764- ``ERRATA_A510_2250311``: This applies errata 2250311 workaround to 765 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 766 r0p3 and r1p0, it is fixed in r1p1. This workaround disables MPMM even if 767 ENABLE_MPMM=1. 768 769- ``ERRATA_A510_2218950``: This applies errata 2218950 workaround to 770 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 771 r0p3 and r1p0, it is fixed in r1p1. 772 773- ``ERRATA_A510_2172148``: This applies errata 2172148 workaround to 774 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 775 r0p3 and r1p0, it is fixed in r1p1. 776 777- ``ERRATA_A510_2347730``: This applies errata 2347730 workaround to 778 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 779 r0p3, r1p0 and r1p1. It is fixed in r1p2. 780 781- ``ERRATA_A510_2371937``: This applies errata 2371937 workaround to 782 Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2, 783 r0p3, r1p0, r1p1, and is fixed in r1p2. 784 785- ``ERRATA_A510_2666669``: This applies errata 2666669 workaround to 786 Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2, 787 r0p3, r1p0, r1p1. It is fixed in r1p2. 788 789- ``ERRATA_A510_2684597``: This applies erratum 2684597 workaround to 790 Cortex-A510 CPU. This needs to be applied to revision r0p0, r0p1, r0p2, 791 r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3. 792 793For Cortex-A715, the following errata build flags are defined : 794 795- ``ERRATA_A715_2701951``: This applies erratum 2701951 workaround to Cortex-A715 796 CPU and affects system configurations that do not use an ARM interconnect 797 IP. This needs to be applied to revisions r0p0, r1p0 and r1p1. It is fixed 798 in r1p2. 799 800DSU Errata Workarounds 801---------------------- 802 803Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ 804Shared Unit) errata. The DSU errata details can be found in the respective Arm 805documentation: 806 807- `Arm DSU Software Developers Errata Notice`_. 808 809Each erratum is identified by an ``ID``, as defined in the DSU errata notice 810document. Thus, the build flags which enable/disable the errata workarounds 811have the format ``ERRATA_DSU_<ID>``. The implementation and application logic 812of DSU errata workarounds are similar to `CPU errata workarounds`_. 813 814For DSU errata, the following build flags are defined: 815 816- ``ERRATA_DSU_798953``: This applies errata 798953 workaround for the 817 affected DSU configurations. This errata applies only for those DSUs that 818 revision is r0p0 (on r0p1 it is fixed). However, please note that this 819 workaround results in increased DSU power consumption on idle. 820 821- ``ERRATA_DSU_936184``: This applies errata 936184 workaround for the 822 affected DSU configurations. This errata applies only for those DSUs that 823 contain the ACP interface **and** the DSU revision is older than r2p0 (on 824 r2p0 it is fixed). However, please note that this workaround results in 825 increased DSU power consumption on idle. 826 827- ``ERRATA_DSU_2313941``: This applies errata 2313941 workaround for the 828 affected DSU configurations. This errata applies for those DSUs with 829 revisions r0p0, r1p0, r2p0, r2p1, r3p0, r3p1 and is still open. However, 830 please note that this workaround results in increased DSU power consumption 831 on idle. 832 833CPU Specific optimizations 834-------------------------- 835 836This section describes some of the optimizations allowed by the CPU micro 837architecture that can be enabled by the platform as desired. 838 839- ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the 840 Cortex-A57 cluster power down sequence by not flushing the Level 1 data 841 cache. The L1 data cache and the L2 unified cache are inclusive. A flush 842 of the L2 by set/way flushes any dirty lines from the L1 as well. This 843 is a known safe deviation from the Cortex-A57 TRM defined power down 844 sequence. Each Cortex-A57 based platform must make its own decision on 845 whether to use the optimization. 846 847- ``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal 848 hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave 849 in a way most programmers expect, and will most probably result in a 850 significant speed degradation to any code that employs them. The Armv8-A 851 architecture (see Arm DDI 0487A.h, section D3.4.3) allows cores to ignore 852 the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this 853 flag enforces this behaviour. This needs to be enabled only for revisions 854 <= r0p3 of the CPU and is enabled by default. 855 856- ``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as 857 ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be 858 enabled only for revisions <= r1p2 of the CPU and is enabled by default, 859 as recommended in section "4.7 Non-Temporal Loads/Stores" of the 860 `Cortex-A57 Software Optimization Guide`_. 861 862- ''A57_ENABLE_NON_CACHEABLE_LOAD_FWD'': This flag enables non-cacheable 863 streaming enhancement feature for Cortex-A57 CPUs. Platforms can set 864 this bit only if their memory system meets the requirement that cache 865 line fill requests from the Cortex-A57 processor are atomic. Each 866 Cortex-A57 based platform must make its own decision on whether to use 867 the optimization. This flag is disabled by default. 868 869- ``NEOVERSE_Nx_EXTERNAL_LLC``: This flag indicates that an external last 870 level cache(LLC) is present in the system, and that the DataSource field 871 on the master CHI interface indicates when data is returned from the LLC. 872 This is used to control how the LL_CACHE* PMU events count. 873 Default value is 0 (Disabled). 874 875GIC Errata Workarounds 876---------------------- 877- ``GIC600_ERRATA_WA_2384374``: This flag applies part 2 of errata 2384374 878 workaround for the affected GIC600 and GIC600-AE implementations. It applies 879 to implementations of GIC600 and GIC600-AE with revisions less than or equal 880 to r1p6 and r0p2 respectively. If the platform sets GICV3_SUPPORT_GIC600, 881 then this flag is enabled; otherwise, it is 0 (Disabled). 882 883-------------- 884 885*Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.* 886 887.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715 888.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639 889.. _CVE-2022-23960: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-23960 890.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html 891.. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/index.html 892.. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html 893.. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf 894.. _Arm DSU Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm138168/index.html 895