feat(morello): add cpuidle support

This patch adds necessary device-tree idle state definitions and enables
relevant platform makefile options.

Co-authored-by: Karl Meakin <karl.meakin@arm.com>
Sig

feat(morello): add cpuidle support

This patch adds necessary device-tree idle state definitions and enables
relevant platform makefile options.

Co-authored-by: Karl Meakin <karl.meakin@arm.com>
Signed-off-by: sahil <sahil@arm.com>
Change-Id: Iaf95867095f0514ec3994b9c9efd9756ed49ef43

show more ...

Merge "fix: bump certifi to version 2023.7.22" into integration

fix: bump certifi to version 2023.7.22

Bump the certifi package to a later version following an advisory [1]
affecting versions >= 2015.4.28, < 2023.7.22.

[1] https://github.com/advisories/GHSA-xqr

fix: bump certifi to version 2023.7.22

Bump the certifi package to a later version following an advisory [1]
affecting versions >= 2015.4.28, < 2023.7.22.

[1] https://github.com/advisories/GHSA-xqr8-7jwr-rhp7

Change-Id: Ida6ff7f0b1228728474de8695dca42303de2b305
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

show more ...

Merge "fix(ti): fix TISCI API changes during refactor" into integration

feat(imx8m): move the gpc reg & macro to a separate header file

move the gpc reg offset, bit define & macro to a separate header
file for code reuse.

This fixes suspend to mem on i.MX8M Plus too, s

feat(imx8m): move the gpc reg & macro to a separate header file

move the gpc reg offset, bit define & macro to a separate header
file for code reuse.

This fixes suspend to mem on i.MX8M Plus too, since the register
layout is different there.

Change-Id: Ibec60c3a68ffa8c378de5334577a7b0e463ca875
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de> # Upgrade to latest, update commit message

show more ...

feat(imx8m): add more dram pll setting

Add DRAM PLL frequency setting for 3732mts & 3733mts.

Change-Id: I74feab2185376bbb84826d7ee79b5e25cbc4d263
Signed-off-by: Marek Vasut <marex@denx.de>

fix(arm/fpga): enable CPU features required for ARMv9.2 cores

Similar to the FVP and QEMU, the Arm FPGA systems come with different
CPU cores, and gain new features over time.

Add a list of ARMv9.2

fix(arm/fpga): enable CPU features required for ARMv9.2 cores

Similar to the FVP and QEMU, the Arm FPGA systems come with different
CPU cores, and gain new features over time.

Add a list of ARMv9.2 features that require TF-A enablement to be usable
from non-secure world. Their existence will be detected at runtime, so
supporting all those features is not required for using the build.

This fixes the Linux kernel booting on a ARMv9.2 FPGA core.

Change-Id: Ie93c32b13ce4f9968081bf38296cd45edad0a928
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

show more ...

Merge changes from topic "xlnx_fix_plat_ocm_base" into integration

* changes:
fix(xilinx): update dtb when dtb address and tf-a ddr flow is used
fix(versal): use correct macro name for ocm base

Merge changes from topic "xlnx_fix_plat_ocm_base" into integration

* changes:
fix(xilinx): update dtb when dtb address and tf-a ddr flow is used
fix(versal): use correct macro name for ocm base address

show more ...

fix(xilinx): update dtb when dtb address and tf-a ddr flow is used

Memory reservation in dtb will be done only when TF-A runs from
ddr and dtb load address is provided.
Otherwise prepare_dtb will si

fix(xilinx): update dtb when dtb address and tf-a ddr flow is used

Memory reservation in dtb will be done only when TF-A runs from
ddr and dtb load address is provided.
Otherwise prepare_dtb will simply return.
Empty definition of prepare_dtb is removed.

Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Change-Id: Ie8a3ec51d60a7389831cfe6a112f722777930623

show more ...

fix(versal): use correct macro name for ocm base address

In absence of definition, PLAT_OCM_BASE is always 0
and IS_TFA_IN_OCM(x) always returns true irrespective
of address passed to it. Reasoning

fix(versal): use correct macro name for ocm base address

In absence of definition, PLAT_OCM_BASE is always 0
and IS_TFA_IN_OCM(x) always returns true irrespective
of address passed to it. Reasoning is as mentioned in
Refer section 4.2.3 in
https://gcc.gnu.org/onlinedocs/gcc-3.0.2/cpp_4.html
Due to this,functionality for reservation of TF-A DDR memory in
dtb is never executed.

Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Change-Id: Iafb6b7c6aec29bba22f8f7a8395f9caf97548157

show more ...

Merge "feat(cpufeat): initialize HFG*_EL2 registers" into integration

Merge changes I03a60d9f,Ib0b38f92 into integration

* changes:
build: sort bootloader image sources
build: allow platform-defined flags

refactor(arm): avoid setting HASH_PREREQUISITES for a build without ROT_KEY

In the absence of ROT_KEY option, there is no need to populate
HASH_PREREQUISITES as the build system uses the hash file s

refactor(arm): avoid setting HASH_PREREQUISITES for a build without ROT_KEY

In the absence of ROT_KEY option, there is no need to populate
HASH_PREREQUISITES as the build system uses the hash file specified by
ARM_ROTPK_HASH directly.

Change-Id: Ib08f53b182b8446bbc430f2608471c7dfdc0e58c
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

show more ...

Merge "refactor(ast2700): update memory layout" into integration

refactor(ast2700): update memory layout

Update the memory layout for both BL31 and BL32 FW based on
the 1GB DRAM space of the AST2700 EVB.

Minor:
- Use SZ_xx macro to define size for better readab

refactor(ast2700): update memory layout

Update the memory layout for both BL31 and BL32 FW based on
the 1GB DRAM space of the AST2700 EVB.

Minor:
- Use SZ_xx macro to define size for better readability

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Change-Id: I6d8285bd675321f615bb67cdd27bb4b6cb4c8b16

show more ...

docs(threat-model): classify threats by mitigating entity

The generic threat model used to list threats in no particular order.

Reorganize threats so that they are grouped by mitigating entity. For

docs(threat-model): classify threats by mitigating entity

The generic threat model used to list threats in no particular order.

Reorganize threats so that they are grouped by mitigating entity. For
example, threats mitigated by the boot firmware (i.e. BL1 and BL2) are
now clubbed together, ditto for those mitigated by the runtime EL3
firmware. Note that some generic threats apply to all firmware images
so these get grouped in their own section as well.

The motivations for this refactoring are the following:

- Clarify the scope of the threats.

In particular, as the boot firmware is typically transient, threats
applying to those images can only be exploited during a short
period of time before the runtime firmware starts.

A note has been added to this effect.

- Helping developers implement mitigations in the right place.

- Some vendors have their own solution for booting their device and
only leverage the runtime firmware from the TF-A project. Thus,
they are not interested in the threat model of TF-A's boot
firmware. Isolating the latter in a specific section helps them
focus on what is important for them.

To avoid unnecessary churn, the threats ids have been kept the same.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: Id8616fd0e4b37cd400b1ad3372beb3455234d4dc

show more ...

docs(threat-model): club RME note with other assumptions

The fact that RME is out of the generic threat model's scope is just
another assumption we make about the target of evaluation so mention
it

docs(threat-model): club RME note with other assumptions

The fact that RME is out of the generic threat model's scope is just
another assumption we make about the target of evaluation so mention
it there.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I839ec5427f36b085148338030e8b1b85191d4245

show more ...

fix(cpus): workaround for Neoverse N2 erratum 2009478

Neoverse N2 erratum 2009478 is a Cat B erratum that applies to
revision r0p0 and is fixed in r0p1. The workaround is to clear
the ED bit for all

fix(cpus): workaround for Neoverse N2 erratum 2009478

Neoverse N2 erratum 2009478 is a Cat B erratum that applies to
revision r0p0 and is fixed in r0p1. The workaround is to clear
the ED bit for all core error records before setting the PWRDN_EN
bit in CPUPWRCTLR_EL1 to request a power down.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ic5ef58c9e795b90026af1d2b09edc0eea3ceee51

show more ...

build: sort bootloader image sources

To avoid duplicate symbol errors when compiling bootloader images which
pull in the same source file multiple times, sort source files before
generating bootload

build: sort bootloader image sources

To avoid duplicate symbol errors when compiling bootloader images which
pull in the same source file multiple times, sort source files before
generating bootloader image build rules in order to remove duplicates.

Change-Id: I03a60d9f752f8fe85f17ec14e265fd4a6223de32
Signed-off-by: Chris Kay <chris.kay@arm.com>

show more ...

build: allow platform-defined flags

Similarly to the earlier patch enabling BL-specific additions to include
directories, preprocessor definitions and toolchain flags, this change
allows platforms t

build: allow platform-defined flags

Similarly to the earlier patch enabling BL-specific additions to include
directories, preprocessor definitions and toolchain flags, this change
allows platforms to add options common to all images.

This is required because some platforms inject dependencies via the
`<platform_def.h>` header, and we don't currently have a clean way to
model that in build system code.

Change-Id: Ib0b38f9236cba6f56745cb3c756dfc81547da8bd
Signed-off-by: Chris Kay <chris.kay@arm.com>

show more ...

Merge "feat(cpus): add support for Nevis CPU" into integration

feat(cpus): add support for Nevis CPU

Adding basic CPU library code to support Nevis CPU

Change-Id: I399cc9b7b2d907b02b76ea2a3e5abb54e28fbf6c
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.co

feat(cpus): add support for Nevis CPU

Adding basic CPU library code to support Nevis CPU

Change-Id: I399cc9b7b2d907b02b76ea2a3e5abb54e28fbf6c
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

show more ...

Merge "fix(ufs): set data segment length" into integration

Merge "chore(npcm845x): remove pauth_helpers.S additions in platform makefile" into integration

chore(npcm845x): remove pauth_helpers.S additions in platform makefile

Currently 'pauth_helpers.S' is added if pauth is enabled from main
level makefile.

Change-Id: I33800e280daea6dba6d11e2c494101b

chore(npcm845x): remove pauth_helpers.S additions in platform makefile

Currently 'pauth_helpers.S' is added if pauth is enabled from main
level makefile.

Change-Id: I33800e280daea6dba6d11e2c494101b369cd8a0b
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

show more ...