feat(mbedtls): update to 3.4.1

Update TF-A documentation to recommend using the latest and greatest
release of mbedTLS library to this date, i.e. version 3.4.1. The
upgrade was successfully tested b

feat(mbedtls): update to 3.4.1

Update TF-A documentation to recommend using the latest and greatest
release of mbedTLS library to this date, i.e. version 3.4.1. The
upgrade was successfully tested by the OpenCI running all existing
test configs, in particular trusted boot and measured boot related
ones.

The reason for this upgrade is simply to obey TF-A's guideline to
always use up-to-date security libraries. mbedTLS 3.4.1 release
notes [1] do not list any changes that should affect TF-A.

[1] https://github.com/Mbed-TLS/mbedtls/releases/tag/v3.4.1

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: Ifc31c2fc825a2fc9ca318ea8baadd51b670e7a4e

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Merge changes from topic "mb/spm+rme-tb-mb-support" into integration

* changes:
fix(fvp): increase the maximum size of Event Log
fix(fvp): increase maximum MMAP and XLAT entries count
fix(arm)

Merge changes from topic "mb/spm+rme-tb-mb-support" into integration

* changes:
fix(fvp): increase the maximum size of Event Log
fix(fvp): increase maximum MMAP and XLAT entries count
fix(arm): add Event Log area behind Trustzone Controller
fix(tbbr): unrecognised 'tos-fw-key-cert' option

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Merge "feat(fvp): capture timestamps in bl stages" into integration

Merge changes from topic "sm/errata_X3" into integration

* changes:
fix(cpus): workaround for Cortex-X3 erratum 2742421
feat(errata_abi): add support for Cortex-X3

Merge "fix(docs): replace deprecated urls under tfa/docs" into integration

feat(stm32mp2): generate stm32 file

To be able to boot, STM32MPU platforms require the BL2 binary (together
with its DT) to be preceded with an STM32 header. Add the required
files and macro to prop

feat(stm32mp2): generate stm32 file

To be able to boot, STM32MPU platforms require the BL2 binary (together
with its DT) to be preceded with an STM32 header. Add the required
files and macro to properly generate this header.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I675de2c5cb733fe9d9e9baf76a941741a06dfac8

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feat(stm32mp2-fdts): add stm32mp257f-ev1 board

Add STM32MP257F Evaluation board support. It embeds a STM32MP257FAI
SoC, with 4GB of DDR4, TSN switch (2+1 ports), 2*USB typeA, 1*USB2
typeC, SNOR Octo

feat(stm32mp2-fdts): add stm32mp257f-ev1 board

Add STM32MP257F Evaluation board support. It embeds a STM32MP257FAI
SoC, with 4GB of DDR4, TSN switch (2+1 ports), 2*USB typeA, 1*USB2
typeC, SNOR OctoSPI, mini PCIe, STPMIC2 for power distribution ...

Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I92da3a7085a4d2f2d606777c4215aed55f77c589

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feat(stm32mp2-fdts): introduce stm32mp25 pinctrl files

Three packages exist for stm32mp25 dies. As ball-out is different
between them, this patch covers those differences by introducing
dedicated pi

feat(stm32mp2-fdts): introduce stm32mp25 pinctrl files

Three packages exist for stm32mp25 dies. As ball-out is different
between them, this patch covers those differences by introducing
dedicated pinctrl dtsi files. Each dtsi pinctrl package file
describes the package ball-out through gpio-ranges.

Available packages are:

STM32MP25xAI: 18*18/FCBGA 172 ios
STM32MP25xAK: 14*14/FCBGA 144 ios
STM32MP25xAL: 10*10/TFBGA 144 ios

It includes also the common file used for pin groups definition.

Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I8500ccccb7a96748f36ffc80edc91da8595f4da8

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feat(stm32mp2-fdts): introduce stm32mp25 SoCs family

STM32MP25 family is composed of 4 SoCs defined as following:

-STM32MP251: common part composed of 1*Cortex-A35, common peripherals
like SDMMC, U

feat(stm32mp2-fdts): introduce stm32mp25 SoCs family

STM32MP25 family is composed of 4 SoCs defined as following:

-STM32MP251: common part composed of 1*Cortex-A35, common peripherals
like SDMMC, UART, SPI, I2C, PCIe, USB3, parallel and DSI display,
1*ETH ...

-STM32MP253: STM32MP251 + 1*Cortex-A35 (dual CPU), a second ETH,
CAN-FD and LVDS display.

-STM32MP255: STM32MP253 + GPU/AI and video encode/decode.
-STM32MP257: STM32MP255 + ETH TSN switch (2+1 ports).

A second diversity layer exists for security features/ A35 frequency:
-STM32MP25xY, "Y" gives information:
-Y = A means A35@1.2GHz + no cryp IP and no secure boot.
-Y = C means A35@1.2GHz + cryp IP and secure boot.
-Y = D means A35@1.5GHz + no cryp IP and no secure boot.
-Y = F means A35@1.5GHz + cryp IP and secure boot.

Change-Id: Icd1351e20b862675d257dede55df190a90acbd59
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(stm32mp2): add console configuration

Use UART driver and fill helpers for crash console.
Add early console setup in bl2_el3_early_platform_setup().

Signed-off-by: Yann Gautier <yann.gautier@st

feat(stm32mp2): add console configuration

Use UART driver and fill helpers for crash console.
Add early console setup in bl2_el3_early_platform_setup().

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ifb39554214dec05dafe4e306f8754e1454cdab61

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feat(st): add RCC registers list

Add a header file listing the registers of Reset and Clock Control
peripheral.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Icc90132d5782eba7e343868

feat(st): add RCC registers list

Add a header file listing the registers of Reset and Clock Control
peripheral.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Icc90132d5782eba7e343868b932a399c1d47c18a

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feat(st-uart): add AARCH64 stm32_console driver

It is an adaptation for AARCH64 of the already existing AARCH32 driver.

Change-Id: Ifabf716a6bd188d2249650a34bbec1a602bcb017
Signed-off-by: Yann Gaut

feat(st-uart): add AARCH64 stm32_console driver

It is an adaptation for AARCH64 of the already existing AARCH32 driver.

Change-Id: Ifabf716a6bd188d2249650a34bbec1a602bcb017
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(st): introduce new platform STM32MP2

This new STMicroelectronics SoC is based on a dual Cortex-A35.
For the moment, only BL2 is compiled with the common parts for ST
platforms.

Change-Id: I1bc

feat(st): introduce new platform STM32MP2

This new STMicroelectronics SoC is based on a dual Cortex-A35.
For the moment, only BL2 is compiled with the common parts for ST
platforms.

Change-Id: I1bc4e6835dba4230359ea9b26d736791e27258aa
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(dt-bindings): add the STM32MP2 clock and reset bindings

Add the associated bindings for device tree and drivers.

Change-Id: I6847df691d4b00f48d2d87a33fbf4ccd62ae5dcf
Signed-off-by: Gabriel Fer

feat(dt-bindings): add the STM32MP2 clock and reset bindings

Add the associated bindings for device tree and drivers.

Change-Id: I6847df691d4b00f48d2d87a33fbf4ccd62ae5dcf
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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docs(changelog): add scopes for STM32MP2

Add stm32mp2 and stm32mp2-fdts scopes.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I4d1918cf40d44244675f58e6967119515edba943

feat(docs): introduce STM32MP2 doc

STM32MP2x is a new family of microprocessors designed by
STMicroelectronics and based on Arm Cortex-A35.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Ch

feat(docs): introduce STM32MP2 doc

STM32MP2x is a new family of microprocessors designed by
STMicroelectronics and based on Arm Cortex-A35.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I741ed0a701a614817a4d0b65d3d6f4e6a79da6a9

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refactor(docs): add a sub-menu for ST platforms

In order to ease introduction of new STM32 MPUs platforms, a dedicated
ST sub-menu (and directory) is created.
The old page is kept, but with an orpha

refactor(docs): add a sub-menu for ST platforms

In order to ease introduction of new STM32 MPUs platforms, a dedicated
ST sub-menu (and directory) is created.
The old page is kept, but with an orphan parameter to avoid build
issues with the docs, and to avoid listing it in the menu. It is
updated to just have links with the new pages.
A new page STM32 MPUs is created to group common options for all STM32
MPUs.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I799b57967d76a985835c7a3d9d6ab21beb44ba40

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refactor(st): move plat_image_load.c

This file is common for ST platforms, move it to plat/st/common/.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I7cefbc7f857d4ea63320042988c86d28

refactor(st): move plat_image_load.c

This file is common for ST platforms, move it to plat/st/common/.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I7cefbc7f857d4ea63320042988c86d28e8a3cc09

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refactor(st): rename PLAT_NB_FIXED_REGS

Rename PLAT_NB_FIXED_REGS to PLAT_NB_FIXED_REGUS.
This avoids confusion with regulators and registers.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
Chang

refactor(st): rename PLAT_NB_FIXED_REGS

Rename PLAT_NB_FIXED_REGS to PLAT_NB_FIXED_REGUS.
This avoids confusion with regulators and registers.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
Change-Id: Idb2de7204fe978ffcdd729e6cbe453e85fd089b5

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refactor(st): move some storage definitions to common part

Those storage macros are common to all STM32MPU chips, move them to
plat/st/common/include/stm32mp_io_storage.h

Signed-off-by: Yann Gautie

refactor(st): move some storage definitions to common part

Those storage macros are common to all STM32MPU chips, move them to
plat/st/common/include/stm32mp_io_storage.h

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Id20ec00ba65edf9ec7a3a89adfda307c954c3cb6

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refactor(st): move SDMMC definitions to driver

Those specific SDMMC definitions are only used in stm32_sdmmc2.c driver.
Move them there.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Chang

refactor(st): move SDMMC definitions to driver

Those specific SDMMC definitions are only used in stm32_sdmmc2.c driver.
Move them there.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Iac7e505e9421aa7630bee8ce6fc2277b98581995

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feat(st-clock): stub fdt_get_rcc_secure_state

The function fdt_get_rcc_secure_state() is only used in BL32.
Put it under flag to avoid compilation errors.

Signed-off-by: Yann Gautier <yann.gautier@

feat(st-clock): stub fdt_get_rcc_secure_state

The function fdt_get_rcc_secure_state() is only used in BL32.
Put it under flag to avoid compilation errors.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: If57c65bef0b1a3f7349527720f94fde26edbb73c

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feat(st-clock): allow aarch64 compilation of STGEN functions

A new local function is created to set STGEN counter value,
that will deal with __aarch64__ flag. And the function
stm32mp_stgen_get_coun

feat(st-clock): allow aarch64 compilation of STGEN functions

A new local function is created to set STGEN counter value,
that will deal with __aarch64__ flag. And the function
stm32mp_stgen_get_counter is adapted for __aarch64__.

Change-Id: I53c21ad11ba5085611a028790e1decbe5994ae50
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(st): allow AARCH64 compilation for common code

Use read_sctlr_el3() for aarch64 code instead of read_sctlr().

Change-Id: I17b5d1f8cb2918de6ab1d2d56c15cabca0ed43fd
Signed-off-by: Yann Gautier <

feat(st): allow AARCH64 compilation for common code

Use read_sctlr_el3() for aarch64 code instead of read_sctlr().

Change-Id: I17b5d1f8cb2918de6ab1d2d56c15cabca0ed43fd
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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refactor(st): rename QSPI macros

To have a more generic code, remove the Q from the *QSPI macros.

Change-Id: I2fa94b54054036c2175df3dfddcb76eec1119ad2
Signed-off-by: Yann Gautier <yann.gautier@st.c

refactor(st): rename QSPI macros

To have a more generic code, remove the Q from the *QSPI macros.

Change-Id: I2fa94b54054036c2175df3dfddcb76eec1119ad2
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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