fix(ufs): performs unsigned shift for doorbell

slot ranges from 0 to 31, left shifting 1 by slot is undefined when slot
is 31

Change-Id: I0c2e6d278ff593cee07736627cd87692f45e2da9
Signed-off-by: Ana

fix(ufs): performs unsigned shift for doorbell

slot ranges from 0 to 31, left shifting 1 by slot is undefined when slot
is 31

Change-Id: I0c2e6d278ff593cee07736627cd87692f45e2da9
Signed-off-by: Anand Saminathan <anans@google.com>

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fix(mmc): initialises response buffer with zeros

if ops->send_cmd in mmc_send_cmd returns a non-zero value, r_data
(resp_data in mmc_device_state) is never populated, so the while
condition in mmc_d

fix(mmc): initialises response buffer with zeros

if ops->send_cmd in mmc_send_cmd returns a non-zero value, r_data
(resp_data in mmc_device_state) is never populated, so the while
condition in mmc_device_state would end up reading the uninitialized
resp_data buffer

Signed-off-by: Anand Saminathan <anans@google.com>
Change-Id: I72d752867c537d49e111e6d149c3cca122f7dc9f

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feat(qemu): add "neoverse-n2" cpu support

Add support to qemu "neoverse-n2" cpu for "qemu" platform.
This one has 2^48 address space so will be used by both systems.

Signed-off-by: Marcin Juszkiewi

feat(qemu): add "neoverse-n2" cpu support

Add support to qemu "neoverse-n2" cpu for "qemu" platform.
This one has 2^48 address space so will be used by both systems.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I9f0fa23a4934d9464379495225e08adc121325b4

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refactor(cpufeat): refactor arch feature build options

Current build infra defaults all cpufeats in defaults.mk and some
mandatory features are enabled in arch_features.mk and optional
arch features

refactor(cpufeat): refactor arch feature build options

Current build infra defaults all cpufeats in defaults.mk and some
mandatory features are enabled in arch_features.mk and optional
arch features are enabled in platform specific makefile.
This fragmentation is sometime confusing to figure out which feature
is tied to which ARCH_MAJOR.ARCH_MINOR.

So, consolidating and grouping them for tracking and enabling makes
more sense. With this change we consolidate all ARCH feature handling
within arch_features.mk and disable all optional features that need
to be enabled to platform makefile.

This is an ongoing series of effort to consolidate and going forward
platform makefile should just specify ARCH_MAJOR and ARCH MINOR and
all mandatory feature should be selected based on arch_features.mk
any optional feature needed by the platform support can be enabled
by platform makefile.

It also makes it easier for platform ports to look upto arch_features.mk
and enable any optional feature that platform may need which are
supported from TF-A.

Change-Id: I18764008856d81414256b6cbabdfa42a16b8040d
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge changes from topic "stm32mp2" into integration

* changes:
feat(stm32mp2): generate stm32 file
feat(stm32mp2-fdts): add stm32mp257f-ev1 board
feat(stm32mp2-fdts): introduce stm32mp25 pinc

Merge changes from topic "stm32mp2" into integration

* changes:
feat(stm32mp2): generate stm32 file
feat(stm32mp2-fdts): add stm32mp257f-ev1 board
feat(stm32mp2-fdts): introduce stm32mp25 pinctrl files
feat(stm32mp2-fdts): introduce stm32mp25 SoCs family
feat(stm32mp2): add console configuration
feat(st): add RCC registers list
feat(st-uart): add AARCH64 stm32_console driver
feat(st): introduce new platform STM32MP2
feat(dt-bindings): add the STM32MP2 clock and reset bindings
docs(changelog): add scopes for STM32MP2
feat(docs): introduce STM32MP2 doc
refactor(docs): add a sub-menu for ST platforms
refactor(st): move plat_image_load.c
refactor(st): rename PLAT_NB_FIXED_REGS
refactor(st): move some storage definitions to common part
refactor(st): move SDMMC definitions to driver
feat(st-clock): stub fdt_get_rcc_secure_state
feat(st-clock): allow aarch64 compilation of STGEN functions
feat(st): allow AARCH64 compilation for common code
refactor(st): rename QSPI macros

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Merge changes from topic "xlnx_mmap_dynamic_dtb" into integration

* changes:
fix(xilinx): dcache flush for dtb region
fix(xilinx): dynamic mmap region for dtb

Merge "feat(qemu): add A55 cpu support for virt" into integration

Merge "fix(plat/arm): do not program DSU CLUSTERPWRDN register" into integration

Merge "fix: bl2 start address for RESET_TO_BL2+ENABLE_PIE" into integration

fix(plat/arm): do not program DSU CLUSTERPWRDN register

This reverts commit 9cf7f355ce8984a4cde970d5f57c913d5247ca6d.

Above mentioned commit was writing to cluster power required bit of
CLUSTERPWRD

fix(plat/arm): do not program DSU CLUSTERPWRDN register

This reverts commit 9cf7f355ce8984a4cde970d5f57c913d5247ca6d.

Above mentioned commit was writing to cluster power required bit of
CLUSTERPWRDN register, which provides an advisory status to the power
controller.
Bit definition indication:
0 : Cluster power is not required when all cores are powered down
1 : Cluster power is required even when all cores are powered down
RESET value of this bit is 0

The current implementation in TF-A just programs this bit to 0 when
cluster power down is done but it never sets it to 1. Which actully
does not change any behaviour as the value of this bit always remains 0.

Ideally this bit has to be set to 1 when a core powers up (as RESET
value is 0) and set it to 0 for any core power down except if its last
man standing, in that case we need to ensure the target power level
from OS is cluster then we can do set it to 0.
There also are some investigation needs to be done to find that whether
we need a explicit message to power controller for turning cluster OFF
or it will happen automatically.

Considering this needs a bit of analysis as well as a platform to test
it on, revert the changes which impact the programming during cluster
power down and just keep register defnition.

Change-Id: I4c4ebedae7ca9cd081fb1e0605b9d906d77614d9
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>

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Merge "fix(fvp): conditionally increase XLAT and MMAP table entries" into integration

fix(xilinx): dcache flush for dtb region

flush dcache region for dtb so that dtb cache entries are first written
to disk and are invalidated afterwards to avoid presence of any stale
dtb related ent

fix(xilinx): dcache flush for dtb region

flush dcache region for dtb so that dtb cache entries are first written
to disk and are invalidated afterwards to avoid presence of any stale
dtb related entry in the dcache.

Change-Id: Ide0ed58f799b35b690ed790c7498ecdc334e02f5
Signed-off-by: Amit Nagal <amit.nagal@amd.com>

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fix(xilinx): dynamic mmap region for dtb

mmap dtb region before usage and unmap it after usage.
overall size(text,data,bss) of dtb gets reduced by
16 bytes in normal flow and 80 bytes in ddr flow.

fix(xilinx): dynamic mmap region for dtb

mmap dtb region before usage and unmap it after usage.
overall size(text,data,bss) of dtb gets reduced by
16 bytes in normal flow and 80 bytes in ddr flow.

Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Change-Id: I411deff57ab141fc2978a2e916aec2d988cb8f9c

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Merge "feat(qemu): add "cortex-a710" cpu support" into integration

fix(fvp): conditionally increase XLAT and MMAP table entries

The XLAT and MMAP table entries are increased as a part of this
patch: 12fe591 , but this is causing failures for some builds,
so conditi

fix(fvp): conditionally increase XLAT and MMAP table entries

The XLAT and MMAP table entries are increased as a part of this
patch: 12fe591 , but this is causing failures for some builds,
so conditionally increased the XLAT and MMAP table entries

Change-Id: I31e8c811bebc767d7187e045a35c9db0eef13ae0
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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fix(corstone-1000): add cpu_helpers.S to platform.mk

Add Platform related dependency in Makefile

Reviewed-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Signed-off-by: Gauri Sahnan <Gauri.S

fix(corstone-1000): add cpu_helpers.S to platform.mk

Add Platform related dependency in Makefile

Reviewed-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Signed-off-by: Gauri Sahnan <Gauri.Sahnan@arm.com>
Change-Id: Idecb84233d3e0c386bf0b7f6d57cbebd38875f28

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feat(qemu): add A55 cpu support for virt

Add support to "cortex-a55" cpu for "qemu" ('virt') platform.

Signed-off-by: Mark-PK Tsai <mark-pk.tsai@mediatek.com>
Change-Id: I2693892be735eda91494b76732

feat(qemu): add A55 cpu support for virt

Add support to "cortex-a55" cpu for "qemu" ('virt') platform.

Signed-off-by: Mark-PK Tsai <mark-pk.tsai@mediatek.com>
Change-Id: I2693892be735eda91494b767322935ddb63c9f48

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fix(auth): don't overwrite pk with converted pk when rotpk is hash

crypto_mod_verify_signature() expects a pointer to the full pk.

In case of stm32mp1 crypto_verify_signature() will call
get_plain_

fix(auth): don't overwrite pk with converted pk when rotpk is hash

crypto_mod_verify_signature() expects a pointer to the full pk.

In case of stm32mp1 crypto_verify_signature() will call
get_plain_pk_from_asn1() on the converted pk which fails.

Fixes: f1e693a775

Signed-off-by: Robin van der Gracht <robin@protonic.nl>
Change-Id: Ia9bdaa10e1b09f9758e5fa608a063b5212c428c3

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feat(qemu): add "cortex-a710" cpu support

Add support to qemu "cortex-a710" cpu for "qemu" platform.

CPU is supported by qemu/virt only as qemu/sbsa-ref memory starts at
2^40 which is limit for Cor

feat(qemu): add "cortex-a710" cpu support

Add support to qemu "cortex-a710" cpu for "qemu" platform.

CPU is supported by qemu/virt only as qemu/sbsa-ref memory starts at
2^40 which is limit for Cortex-A710.

Switched 'qemu' platform to be built as armv8.5 to cover features of
new cpu core.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I035790eac41b2caf7f13167e53f48c16f0827754

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feat(cpufeat): add memory retention bit define for CLUSTERPWRDN

Bit1 in the CLUSTERPWRDN register is used to indicate on CLUSTERPACTIVE
that memory retention is required or not. It can be used for
L

feat(cpufeat): add memory retention bit define for CLUSTERPWRDN

Bit1 in the CLUSTERPWRDN register is used to indicate on CLUSTERPACTIVE
that memory retention is required or not. It can be used for
L3 cache memory retention support.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I1c53c90ae3dfbed3be7e5b2b79f2c3565db81012

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fix: bl2 start address for RESET_TO_BL2+ENABLE_PIE

BL31 image has grown with feature addition over time. In particular the
RESET_TO_BL2 + ENABLE_PIE + DEBUG combination of options lead to BL31
image

fix: bl2 start address for RESET_TO_BL2+ENABLE_PIE

BL31 image has grown with feature addition over time. In particular the
RESET_TO_BL2 + ENABLE_PIE + DEBUG combination of options lead to BL31
image overlap head of BL2 image. In this configuration BL2 is meant to
stay resident as PE reset occurs from BL2. Apply changes similar to [1]
such that BL2 start address is pushed forward and leaves more room for
BL31 end of image.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/15486/9/include/plat/arm/common/arm_def.h#530

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I027e23780fb77ca9fe81aa47231da649c7a030ee

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Merge "refactor(arm): avoid setting HASH_PREREQUISITES for a build without ROT_KEY" into integration

Merge "feat(mbedtls): update to 3.4.1" into integration

chore: remove MULTI_CONSOLE_API references

MULTI_CONSOLE_API have been removed long time ago by commit 5b6ebeec9c99
("Remove MULTI_CONSOLE_API flag and references to it") that's why remove
reference

chore: remove MULTI_CONSOLE_API references

MULTI_CONSOLE_API have been removed long time ago by commit 5b6ebeec9c99
("Remove MULTI_CONSOLE_API flag and references to it") that's why remove
references in platform.mk files and also in one rst which is not valid
anymore.

Change-Id: I45f8e7db0a14ce63de62509100d8159b7aca2657
Signed-off-by: Michal Simek <michal.simek@amd.com>

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Merge "docs(maintainers): add maintainers for i.MX9 SoCs" into integration