fix(intel): update fcs crypto init code to check for mode

The shall code only limit ECB, CBC and CTR mode to flow through the init
function. Anything other than that, the code shall reject to preven

fix(intel): update fcs crypto init code to check for mode

The shall code only limit ECB, CBC and CTR mode to flow through the init
function. Anything other than that, the code shall reject to prevent
security vulnerability.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I702ce90e229188830f8936bee2999610e9559b8b

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Merge changes I038dc2bf,Iade15431 into integration

* changes:
fix(rcar3): change RAM protection configurations
fix(rcar3): fix load address range check

Merge "fix(rcar3-drivers): check loaded NS image area" into integration

fix(rcar3): change RAM protection configurations

Change RAM protection control not to overwrite the images by DSMAC.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-o

fix(rcar3): change RAM protection configurations

Change RAM protection control not to overwrite the images by DSMAC.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I038dc2bf90e721692d392ea4de5441647aa62029
---
Marek: - Move axi DRAM out and merge AXI_SPTCR15 setting into it
- Set AXI_SPTCR1 from 0x0E000E0EU to 0x0E000000U to let
TEE pick TFA DT

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fix(rcar3-drivers): check loaded NS image area

Check if next NS image invades a previous loaded image.
Correct non secure image area to avoid loading a NS image to secure

Move GZ compressed payload

fix(rcar3-drivers): check loaded NS image area

Check if next NS image invades a previous loaded image.
Correct non secure image area to avoid loading a NS image to secure

Move GZ compressed payload at 32 * compressed payload size offset,
so it is loaded in non-secure area and can be decompressed into
non-secure area too. It is unlikely that the up to 2 MiB compressed
BL33 blob would decompress to payload larger than 64 MiB .

Signed-off-by: Tobias Rist <tobias.rist@joynext.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Fix for compressed BL33
Change-Id: I52fd556aab50687e4791e5dbc45d425f802c8757

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fix(rcar3): fix load address range check

Fixed the check of the address range which the program is loaded to.
Use the addresses and sizes in the BL31 and BL32 certificates to check
that they are wit

fix(rcar3): fix load address range check

Fixed the check of the address range which the program is loaded to.
Use the addresses and sizes in the BL31 and BL32 certificates to check
that they are within the range of the target address and size
defined inside the TF-A.
It also uses the addresses and sizes in the BL33x certificates to check
that they are outside the protected area defined inside the TF-A.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Code clean up
Change-Id: Iade15431fc86587489fb0ca9106f6baaf7e926e2

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Merge changes from topic "sm/erratum" into integration

* changes:
fix(cpus): workaround for Cortex-A520 erratum 2630792
fix(cpus): workaround for Cortex-X2 erratum 2778471
fix(cpus): workaroun

Merge changes from topic "sm/erratum" into integration

* changes:
fix(cpus): workaround for Cortex-A520 erratum 2630792
fix(cpus): workaround for Cortex-X2 erratum 2778471
fix(cpus): workaround for Cortex-A710 erratum 2778471

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fix(cpus): workaround for Cortex-A520 erratum 2630792

Cortex-A520 erratum is a Cat B erratum that applies
to revisions r0p0 and r0p1 and is still open.
The workaround is to set CPUACTLR_EL1[38] to 1

fix(cpus): workaround for Cortex-A520 erratum 2630792

Cortex-A520 erratum is a Cat B erratum that applies
to revisions r0p0 and r0p1 and is still open.
The workaround is to set CPUACTLR_EL1[38] to 1.

SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2444153/latest

Change-Id: Idb6f32f680ee1378a57c2d2f809ea847fffe5910
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(cpus): workaround for Cortex-X2 erratum 2778471

Cortex-X2 erratum 2778471 is a Cat B erratum that applies
to revisions r0p1, r1p0, r2p0 and r2p1 and is still open.
The workaround is to set CPUAC

fix(cpus): workaround for Cortex-X2 erratum 2778471

Cortex-X2 erratum 2778471 is a Cat B erratum that applies
to revisions r0p1, r1p0, r2p0 and r2p1 and is still open.
The workaround is to set CPUACTLR3_EL1[47] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest

Change-Id: Ia95f0e276482283bf50e06c58c2bc5faab3f62c6
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(cpus): workaround for Cortex-A710 erratum 2778471

Cortex-A710 erratum 2778471 is a Cat B erratum that applies
to revisions r0p1, r1p0, r2p0 and r2p1 and is still open.
The workaround is to set C

fix(cpus): workaround for Cortex-A710 erratum 2778471

Cortex-A710 erratum 2778471 is a Cat B erratum that applies
to revisions r0p1, r1p0, r2p0 and r2p1 and is still open.
The workaround is to set CPUACTLR3_EL1[47] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775101/latest

Change-Id: Id3bb4a2673e41ff237682e46784d37752daf2f83
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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Merge "fix(sgi): apply workarounds for N2 CPU erratum" into integration

fix(sgi): apply workarounds for N2 CPU erratum

For RD-N2 and variant platforms, enable workarounds available for the
N2 CPU erratum.

Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id

fix(sgi): apply workarounds for N2 CPU erratum

For RD-N2 and variant platforms, enable workarounds available for the
N2 CPU erratum.

Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: Ib0240f56813a913309e5a6a1902e2990979e9617

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Merge changes If2743827,I163f8169,I97a69650 into integration

* changes:
feat(imx8m): add 3600 MTps DDR PLL rate
fix(imx8m): align 3200 MTps rate with U-Boot
fix(imx8m): handle 3734 in addition

Merge changes If2743827,I163f8169,I97a69650 into integration

* changes:
feat(imx8m): add 3600 MTps DDR PLL rate
fix(imx8m): align 3200 MTps rate with U-Boot
fix(imx8m): handle 3734 in addition to 3733 and 3732 MTps rates

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fix(cpus): fix incorrect AMU trap settings for N2 CPU

The TAM bits of CPTR_EL2 and CPTR_EL3 are incorrectly set in the reset
handling sequence of the Neoverse N2 CPU. As these bits are set, any
acce

fix(cpus): fix incorrect AMU trap settings for N2 CPU

The TAM bits of CPTR_EL2 and CPTR_EL3 are incorrectly set in the reset
handling sequence of the Neoverse N2 CPU. As these bits are set, any
access of AMU registers from EL0/EL1 and EL2 respectively are
incorrectly trapped to a higher EL. Fix this by clearing the TAM bits in
both the CPTR_EL2 and CPTR_EL3 registers.

Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: I357b16dfc7d7367b8a0c8086faac28f3e2866cd8

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Merge "feat(versal-net): add bufferless IPI Support" into integration

Merge "build(versal-net): reorganize platform source files" into integration

Merge changes from topic "ns/spmc_at_el3" into integration

* changes:
feat(rdn2): update power message value to 0
feat(el3-spmc): add support to handle power mgmt calls for s-el0 sp

feat(rdn2): update power message value to 0

Standalone MM used by RD-N2 platfrom does not have power messaging
support. Set the value to 0.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Ch

feat(rdn2): update power message value to 0

Standalone MM used by RD-N2 platfrom does not have power messaging
support. Set the value to 0.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: Icdb16ea1976ce751071ce3df0e4bd86f3fb8ab8b

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feat(el3-spmc): add support to handle power mgmt calls for s-el0 sp

Add support to setup S-EL0 SP context during power management power on
procedure. In case of power on, initialise the context data

feat(el3-spmc): add support to handle power mgmt calls for s-el0 sp

Add support to setup S-EL0 SP context during power management power on
procedure. In case of power on, initialise the context data structure
for the secure world on the current CPU.
The S-EL0 SP does not support power message. Add the check to make
sure that it does not subscribe to any power messages.

Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: Ic9cf98cd15b6ee5d86d071a52bc0973677049df3

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Merge "fix(tc): guard PSA crypto headers under TF-M test-suite define" into integration

fix(marvell-tools): include mbedtls/version.h before use

mbedtls/version.h needs to be included before the use of any
mbedtls config variables.

Fixes a build failure regression from commit a8eadc51

fix(marvell-tools): include mbedtls/version.h before use

mbedtls/version.h needs to be included before the use of any
mbedtls config variables.

Fixes a build failure regression from commit a8eadc51a.

Change-Id: Idd955d7955b0a55ffd127f31053335542cb15e22
Signed-off-by: Henrik Nordstrom <henrik.nordstrom@addiva.se>

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Merge "fix(intel): update HPS bridges for Agilex5 SoC FPGA" into integration

fix(tc): guard PSA crypto headers under TF-M test-suite define

The inclusion of PSA crypto headers is specifically required
during the building of TF-M test-suite platform tests for TC2.
Hence guard

fix(tc): guard PSA crypto headers under TF-M test-suite define

The inclusion of PSA crypto headers is specifically required
during the building of TF-M test-suite platform tests for TC2.
Hence guarded the inclusion of these headers under the define
PLATFORM_TEST_TFM_TESTSUITE.

Change-Id: Ia5dcadb93f308d2248d9768d373a87316ceb983c
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "feat(tc): provide a mock mbedtls-random generation function" into integration

feat(versal-net): add bufferless IPI Support

There exist inter-processor interrupts on Versal-Net that do not have
corresponding message buffers. These bufferless IPI's on Versal NET
SOC are added t

feat(versal-net): add bufferless IPI Support

There exist inter-processor interrupts on Versal-Net that do not have
corresponding message buffers. These bufferless IPI's on Versal NET
SOC are added to static IPI Tables.

In hardware description there exists two IPI's called 'IPI6' without
buffers that have respective system interrupt values 95 and 101. For
these append the string '_95' or '_101' to denote the difference for
each.

Change-Id: I22bf1a68cb0ed68913eb868f1c197856fc7d82d5
Signed-off-by: Ben Levinsky <ben.levinsky@amd.com>

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