Merge changes Ifbc5ab02,Ib9002609,I0276257d into integration

* changes:
fix(fvp): initialise the event log's size to avoid using gibberish values
fix(tsp): keep the tsp D128 unaware, not the dis

Merge changes Ifbc5ab02,Ib9002609,I0276257d into integration

* changes:
fix(fvp): initialise the event log's size to avoid using gibberish values
fix(tsp): keep the tsp D128 unaware, not the dispatcher
fix(dice): prevent compiler warnings

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Merge "docs: update TF-A May'26 release dates" into integration

Merge "feat(rcar): deduplicate PWRC timer" into integration

Merge changes I24209ac0,I1caf6cc6 into integration

* changes:
feat(rcar): deduplicate PWRC SRAM trampoline
feat(rcar): deduplicate stack protector

Merge "fix(el3-spmc): set NS bit by default and clear it as needed" into integration

Merge "fix(cm): correctly restore BL2's context" into integration

Merge "feat(cpufeat): enable FEAT_PFAR support" into integration

docs: update TF-A May'26 release dates

Tentatively updating the plan for TF-A v2.15 release in May'26.

Change-Id: I43de74567c57139023844a55ca90d354b6cc680d
Signed-off-by: Govindraj Raja <govindraj.

docs: update TF-A May'26 release dates

Tentatively updating the plan for TF-A v2.15 release in May'26.

Change-Id: I43de74567c57139023844a55ca90d354b6cc680d
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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feat(cpufeat): enable FEAT_PFAR support

Implement support for FEAT_PFAR, which introduces the PFAR_ELx system
register, recording the faulting physical address for some aborts.
Those system register

feat(cpufeat): enable FEAT_PFAR support

Implement support for FEAT_PFAR, which introduces the PFAR_ELx system
register, recording the faulting physical address for some aborts.
Those system registers are trapped by the SCR_EL3.PFARen bit, so set the
bit for the non-secure world context to allow OSes to use the feature.

This is controlled by the ENABLE_FEAT_PFAR build flag, which follows the
usual semantics of 2 meaning the feature being runtime detected.
Let the default for this flag be 0, but set it to 2 for the FVP.

Change-Id: I5c9ae750417e75792f693732df3869e02b6e4319
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "fix(xilinx): limit pm_feature_check deprecation warning to once per boot" into integration

fix(xilinx): limit pm_feature_check deprecation warning to once per boot

The deprecation warning in pm_feature_check() is being displayed
multiple times during boot, causing log spam.

Modify the wa

fix(xilinx): limit pm_feature_check deprecation warning to once per boot

The deprecation warning in pm_feature_check() is being displayed
multiple times during boot, causing log spam.

Modify the warning to display only once per boot session by using
a static boolean flag. This maintains the deprecation notification
while reducing log verbosity.

Change-Id: Ie2ae265b0e0b4d08c6341f1870258b970f5a1fc7
Signed-off-by: Devanshi Chauhan <Devanshi.ChauhanAlpeshbhai@amd.com>

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fix(el3-spmc): set NS bit by default and clear it as needed

EL3-SPMC currently only supports sharing and lending memory
from NS to the secure world (DONATE is not supported).
That means that the NS

fix(el3-spmc): set NS bit by default and clear it as needed

EL3-SPMC currently only supports sharing and lending memory
from NS to the secure world (DONATE is not supported).
That means that the NS bit should always be set,
except for a few cases:
* The operation is a LEND (NS->S), or
* The NS bit is not supported, i.e., v1.0 where the bit
was not explicitly negotiated.

Change-Id: I00966a552906ebbe2675b4352afe5e85387e5775
Signed-off-by: Andrei Homescu <ahomescu@xwf.google.com>

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Merge "feat(cpufeat): enable FEAT_AIE support" into integration

fix(fvp): initialise the event log's size to avoid using gibberish values

The event log's DT bindings only specify the lower 32 bits of the event
log's size, but the size is held in a 64 bit variabl

fix(fvp): initialise the event log's size to avoid using gibberish values

The event log's DT bindings only specify the lower 32 bits of the event
log's size, but the size is held in a 64 bit variable on stack. When
conditions are right, the uninitialised upper 32 bits may contain
gibberish that throws off our computations, leading to faults.

Change-Id: Ifbc5ab027aac4e8899fea962656b07960b9b00b9
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(tsp): keep the tsp D128 unaware, not the dispatcher

The tspd is a core part of the el3 runtime and it must behave the same
way, i.e. it must handle FEAT_D128. The tsp on the other hand is a bit

fix(tsp): keep the tsp D128 unaware, not the dispatcher

The tspd is a core part of the el3 runtime and it must behave the same
way, i.e. it must handle FEAT_D128. The tsp on the other hand is a bit
more special and can have carveouts, which patch f3e2b4997 added.

That incorrectly did it for the tspd instead of the tsp, so fix that.

Change-Id: Ib9002609ef9c66b0d1fcc5b3a9f012376d0c3bf4
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(dice): prevent compiler warnings

LTO builds make the compiler observe possible unitialised accesses.
That's not the case, but calm it down with a 0. It also doesn't like the
declaration mismatch

fix(dice): prevent compiler warnings

LTO builds make the compiler observe possible unitialised accesses.
That's not the case, but calm it down with a 0. It also doesn't like the
declaration mismatch in tc so bring it in line.

Change-Id: I0276257d05d1cb1d4f7e1e0d914c48c8ab3d308d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes I17523700,Ic05f3227,Id9c509a5 into integration

* changes:
feat(qemu): add support for FEAT_GCS
feat(qemu): add support for FEAT_SxPxE
feat(qemu): add support for FEAT_TCR2 and FE

Merge changes I17523700,Ic05f3227,Id9c509a5 into integration

* changes:
feat(qemu): add support for FEAT_GCS
feat(qemu): add support for FEAT_SxPxE
feat(qemu): add support for FEAT_TCR2 and FEAT_SCTLR2

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fix(locks): mark spin_trylock as a public function

This patch updates spinlock.S to make the spin_trylock helper
function as public. This will allow other parts of the TF-A
to use this function.

Ch

fix(locks): mark spin_trylock as a public function

This patch updates spinlock.S to make the spin_trylock helper
function as public. This will allow other parts of the TF-A
to use this function.

Change-Id: Id264a36490707a9377a221ed2b5bd27ca90bf459
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge changes I92c3e293,I95149f5e into integration

* changes:
fix(imx): match function parameters to declaration
fix(intel): match declaration with definition

Merge "fix(rcar3): clear TCR_EL1 at the BL2 entry point" into integration

feat(qemu): add support for FEAT_GCS

Auto-detect FEAT_GCS and enable it when the platform supports it.
This is needed for Linux under QEMU 10.2

Change-Id: I175237006d3808bc058499a34357918674a0c561

feat(qemu): add support for FEAT_GCS

Auto-detect FEAT_GCS and enable it when the platform supports it.
This is needed for Linux under QEMU 10.2

Change-Id: I175237006d3808bc058499a34357918674a0c561
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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feat(qemu): add support for FEAT_SxPxE

Auto-detect the POE and PIE features and enable them when the platform
supports them. This is needed for Linux under QEMU 10.2.

Change-Id: Ic05f3227e61386b06a

feat(qemu): add support for FEAT_SxPxE

Auto-detect the POE and PIE features and enable them when the platform
supports them. This is needed for Linux under QEMU 10.2.

Change-Id: Ic05f3227e61386b06a1deffce8678048aed456b1
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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feat(qemu): add support for FEAT_TCR2 and FEAT_SCTLR2

QEMU supports this since 10.1.
ENABLE_FEAT_TCR2 is needed to boot a Linux guest.
ENABLE_FEAT_SCTLR2 is needed to boot a Linux nested guest.

Cha

feat(qemu): add support for FEAT_TCR2 and FEAT_SCTLR2

QEMU supports this since 10.1.
ENABLE_FEAT_TCR2 is needed to boot a Linux guest.
ENABLE_FEAT_SCTLR2 is needed to boot a Linux nested guest.

Change-Id: Id9c509a530fb5d0df9955f80ef26992d5bea1191
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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Merge "fix(scmi): change error code output for wrong ids" into integration

feat(rcar): deduplicate plat_crash_print_regs

The plat_crash_print_regs code is functionally identical between
Renesas R-Car Gen3 and R-Car Gen4, deduplicate the code. Split
plat_crash_print_regs in

feat(rcar): deduplicate plat_crash_print_regs

The plat_crash_print_regs code is functionally identical between
Renesas R-Car Gen3 and R-Car Gen4, deduplicate the code. Split
plat_crash_print_regs into plat_macros_cci.S and move the Gen3
specific plat_print_gic_regs macro into plat_macros_gic.S so it
can be pulled in only on R-Car Gen3.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I82beb663e769e7b33a79b992da9f70db7bad2d51

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