Merge "fix(intel): update stream id to non-secure for SDM" into integration

Merge "fix(intel): revert sys counter to 400MHz" into integration

Merge "fix(errata): check for SCU before accessing DSU" into integration

fix(errata): check for SCU before accessing DSU

The DSU contains system control registers in the SCU and L3 logic to
control the functionality of the cluster. If "DIRECT CONNECT" L3 memory
system va

fix(errata): check for SCU before accessing DSU

The DSU contains system control registers in the SCU and L3 logic to
control the functionality of the cluster. If "DIRECT CONNECT" L3 memory
system variant is used, there won't be any L3 cache, snoop filter, and
SCU logic present hence no system control register will be present.
Hence check SCU presence before accessing DSU register for DSU_2313941
errata.

(commit message taken from commit
942013e1dd57429432cd71cfe121d702e3c52465 by Pramod Kumar
<pramod.kumar@broadcom.com> just errata number changed)

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I38cee6085d6e49ba23de95b3de08bc98798ab2b3

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Merge changes from topic "mb/deprecate-rss-for-fvp" into integration

* changes:
refactor(fvp): remove RSS usage
refactor(rss)!: remove PLAT_RSS_NOT_SUPPORTED build option

Merge changes from topic "ns/spmc_at_el3" into integration

* changes:
fix(sgi): reduce cper buffer carveout size
fix(sgi): increase BL31 carveout size

Merge "feat(mediatek): remove bl32 flag for mtk_bl" into integration

Merge "docs(changelog): changelog for v2.10 release" into integration

docs(changelog): changelog for v2.10 release

Added changelog for v2.10 release.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

docs(changelog): changelog for v2.10 release

Added changelog for v2.10 release.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: Id06263047fcc1ec60e82f85cd09e2e4bc95830f5

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feat(security): add support for SLS mitigation

This patch enables support for the gcc compiler option "-mharden-sls",
the default is not to use this option. Setting HARDEN_SLS=1 sets
"-mharden-sls=a

feat(security): add support for SLS mitigation

This patch enables support for the gcc compiler option "-mharden-sls",
the default is not to use this option. Setting HARDEN_SLS=1 sets
"-mharden-sls=all" that enables all hardening against straight line
speculation.

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I59f5963c22431571f5aebe7e0c5642b32362f4c9

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fix(cpus): workaround for Neoverse V2 erratum 2662553

Neoverse V2 erratum 2662553 is a Cat B erratum that applies to all
revisions <= r0p1 and is fixed in r0p2.
The workaround is to set L2 TQ size s

fix(cpus): workaround for Neoverse V2 erratum 2662553

Neoverse V2 erratum 2662553 is a Cat B erratum that applies to all
revisions <= r0p1 and is fixed in r0p2.
The workaround is to set L2 TQ size statically to it's full size.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2332927/latest

Change-Id: I3bc43e7299c17db8a6771a547515ffb2a172fa0f
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

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Merge "Revert "docs(changelog): changelog for v2.10 release"" into integration

Revert "docs(changelog): changelog for v2.10 release"

This reverts commit 0abbfab320344d4f2110e95d64863a3e82a51ec9.

Reason for revert: Changelog was based on rc0 tag but we got few more patches aft

Revert "docs(changelog): changelog for v2.10 release"

This reverts commit 0abbfab320344d4f2110e95d64863a3e82a51ec9.

Reason for revert: Changelog was based on rc0 tag but we got few more patches after that which were not captured.

Change-Id: I9829f2b6dc09f0bd5c538845cbae051f6e4c8a75

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fix(sgi): reduce cper buffer carveout size

Reduce the size of the CPER buffer as it is overlapping with SP's heap
region.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: Iaea75a1f

fix(sgi): reduce cper buffer carveout size

Reduce the size of the CPER buffer as it is overlapping with SP's heap
region.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: Iaea75a1ffb50ecf0223594fe8bffcebc16da7eab

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fix(sgi): increase BL31 carveout size

With SPMC at el3 enabled on rdn2cfg2 configuration BL31 needs more
memory region to accommodate increased xlat table size.

Increase the size by 16K.

Signed-of

fix(sgi): increase BL31 carveout size

With SPMC at el3 enabled on rdn2cfg2 configuration BL31 needs more
memory region to accommodate increased xlat table size.

Increase the size by 16K.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: Ib235fe35d53a9b85a5ce0a29f2ec4cc3bd85ded9

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Merge "docs(threat-model): add a threat model for TF-A with Arm CCA" into integration

Merge "refactor(tc): deprecate Arm TC1 FVP platform" into integration

fix(cpus): workaround for Cortex-A78C erratum 2743232

Cortex-A78C erratum 2743232 is a Cat B erratum that applies
to revisions r0p1 and r0p2 and is still open.
The workaround is to set CPUACTLR5_EL1

fix(cpus): workaround for Cortex-A78C erratum 2743232

Cortex-A78C erratum 2743232 is a Cat B erratum that applies
to revisions r0p1 and r0p2 and is still open.
The workaround is to set CPUACTLR5_EL1[56:55] to 2'b01.

SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2004089/latest

Change-Id: Ic62579c2dd69b7a8cbbeaa936f45b2cc9436439a
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(cpus): workaround for Neoverse V1 erratum 2348377

Neoverse V1 erratum 2348377 is a Cat B erratum that applies to
all revisions <= r1p1 and is fixed in r1p2. The workaround is to
set CPUACTLR5_EL

fix(cpus): workaround for Neoverse V1 erratum 2348377

Neoverse V1 erratum 2348377 is a Cat B erratum that applies to
all revisions <= r1p1 and is fixed in r1p2. The workaround is to
set CPUACTLR5_EL1[61] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1401781/latest

Change-Id: Ica402494f78811c85e56a262e1f60b09915168fe
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(cpus): workaround for Cortex-X3 erratum 2779509

Cortex-X3 erratum 2779509 is a Cat B erratum that applies to
all revisions <= r1p1 and is fixed in r1p2. The workaround is
to set chicken bit CPUA

fix(cpus): workaround for Cortex-X3 erratum 2779509

Cortex-X3 erratum 2779509 is a Cat B erratum that applies to
all revisions <= r1p1 and is fixed in r1p2. The workaround is
to set chicken bit CPUACTLR3_EL1[47], this might have a small
impact on power and has negligible impact on performance.

SDEN documentation:
https://developer.arm.com/documentation/2055130/latest

Change-Id: Id92dbae6f1f313b133ffaa018fbf9c078da55d75
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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Merge "docs(changelog): changelog for v2.10 release" into integration

refactor(tc): deprecate Arm TC1 FVP platform

Arm has made the strategic decision to deprecate the TC1 platform.
Consequently, software development and the creation of fast models
for the TC1 platfor

refactor(tc): deprecate Arm TC1 FVP platform

Arm has made the strategic decision to deprecate the TC1 platform.
Consequently, software development and the creation of fast models
for the TC1 platform have been officially discontinued.
The TC1 platform, now considered obsolete, has been succeeded by
the TC2 platform. It's noteworthy that the TC2 platform is already
integrated and supported in both TF-A and CI repositories.

Change-Id: Ia196a5fc975b4dbf3c913333daf595199968d95d
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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docs(changelog): changelog for v2.10 release

Change-Id: I44b88c3232d099b85ff71ee14c4918c4f8180146
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

Merge changes from topic "hm/rt-instr" into integration

* changes:
docs(juno): update PSCI instrumentation data
docs(n1sdp): update N1SDP PSCI instrumentation data

Merge "docs: add a section for experimental build options" into integration