refactor(css): support multiple SDS regions

Extend the SDS driver to be able to handle multiple
SDS regions:
- AP-SCP
- AP-RSS

Change-Id: Id303840b248c383b3f960227cbf6333d1cc75e65
Signed-off-by:

refactor(css): support multiple SDS regions

Extend the SDS driver to be able to handle multiple
SDS regions:
- AP-SCP
- AP-RSS

Change-Id: Id303840b248c383b3f960227cbf6333d1cc75e65
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Signed-off-by: David Vincze <david.vincze@arm.com>

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Merge "fix(qemu): disable FEAT_SB" into integration

fix(gpt): use DC CIGDPAPA when MTE2 is implemented

Use cache clean and invalidate of data and allocation tags by PA to PoPA
maintenance instruction (dc cigdpapa) in the GPT library upon changing
the

fix(gpt): use DC CIGDPAPA when MTE2 is implemented

Use cache clean and invalidate of data and allocation tags by PA to PoPA
maintenance instruction (dc cigdpapa) in the GPT library upon changing
the PAS for a memory region. This is required to flush allocation tags
when MTE2 (and above) is implemented.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I4b70afb297f693b1d446839607922c47111ce063

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Merge "feat(mte): add mte2 feat" into integration

feat(mte): add mte2 feat

Add support for feat mte2. tfsr_el2 is available only with mte2,
however currently its context_save/restore is done with mte rather than
mte2, so introduce 'is_feat_mte2_sup

feat(mte): add mte2 feat

Add support for feat mte2. tfsr_el2 is available only with mte2,
however currently its context_save/restore is done with mte rather than
mte2, so introduce 'is_feat_mte2_supported' to check mte2.

Change-Id: I108d9989a8f5b4d1d2f3b9865a914056fa566cf2
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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test(fvp): remove `FVP_Foundation` model support

This model has been subsumed by the `FVP_Base` model, which is now
available publicly. We no longer have a need to test the Foundation
model, and can

test(fvp): remove `FVP_Foundation` model support

This model has been subsumed by the `FVP_Base` model, which is now
available publicly. We no longer have a need to test the Foundation
model, and can shave off a few minutes of CI time by removing it.

Change-Id: Iaa0f23f2efd9ba431d06c8da2be14b76f6974b0a
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge changes from topic "revert-ti-dm-workaround" into integration

* changes:
Revert "fix(ti): do not take system power reference in bl31_platform_setup()"
refactor(ti): remove ti_sci_init func

Merge changes from topic "revert-ti-dm-workaround" into integration

* changes:
Revert "fix(ti): do not take system power reference in bl31_platform_setup()"
refactor(ti): remove ti_sci_init function
fix(k3): increment while reading trail bytes

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Merge "refactor(gicv3): introducing is_valid_interrupt, a new helper utility" into integration

Merge "feat(fvp): remove left-over RSS usage" into integration

feat(fvp): remove left-over RSS usage

Remove any residual RSS usage in the FVP platform, complementing the
changes made in commit dea307fd6cca2dad56867e757804224a8654bc38.

Signed-off-by: Manish V B

feat(fvp): remove left-over RSS usage

Remove any residual RSS usage in the FVP platform, complementing the
changes made in commit dea307fd6cca2dad56867e757804224a8654bc38.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I9ced272503456361610ec0c7783d270349233926

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Merge "fix(build): properly manage versions in .versionrc.js" into integration

Merge "fix(build): move comment for VERSION_PATCH" into integration

Merge "docs(auth): add more information about CoTs" into integration

docs(auth): add more information about CoTs

Explain that platforms are free to define their own Chain of Trust (CoT)
based on their needs but default ones are provided in TF-A source code:
TBBR, dua

docs(auth): add more information about CoTs

Explain that platforms are free to define their own Chain of Trust (CoT)
based on their needs but default ones are provided in TF-A source code:
TBBR, dualroot and CCA.

Give a brief overview of the use case for each of these CoTs.

Simplified diagrams are also provided for the TBBR and dualroot CoTs -
CCA CoT is missing such a diagram right now, it should be provided as a
future improvement.

Also do some cosmetic changes along the way.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I7c4014d4d12d852b0ae5632ba9c71a9ad266080a

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Merge "docs(auth): add missing AUTH_PARAM_NV_CTR value" into integration

fix(build): properly manage versions in .versionrc.js

To properly update pyproject.toml & docs/conf.py, we should manage
several digits for version number (the 10 for VERSION_MINOR), and the
VERSION

fix(build): properly manage versions in .versionrc.js

To properly update pyproject.toml & docs/conf.py, we should manage
several digits for version number (the 10 for VERSION_MINOR), and the
VERSION_PATCH.

Change-Id: I612338fd2896f3fe614f23d14f56d58d43318a11
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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fix(build): move comment for VERSION_PATCH

Having a comment at the end of VERSION_PATCH definition line prevent
the release script to work properly. Move it on the previous line.

Signed-off-by: Yan

fix(build): move comment for VERSION_PATCH

Having a comment at the end of VERSION_PATCH definition line prevent
the release script to work properly. Move it on the previous line.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I4008ccbccd512edf33f67c645b38937ad1af9777

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fix(qemu): disable FEAT_SB

qemu/qemu_sbsa platforms support wide selection of cpu cores. From
Cortex-A57 (v8.0) to Neoverse-N2 (v9.0) one. Only the last one (and
'max' which supports everything poss

fix(qemu): disable FEAT_SB

qemu/qemu_sbsa platforms support wide selection of cpu cores. From
Cortex-A57 (v8.0) to Neoverse-N2 (v9.0) one. Only the last one (and
'max' which supports everything possible) supports FEAT_SB.

Runtime check for ENABLE_FEAT_SB does not work in our case and we want
to have working platform.

Change-Id: Ic27d5af20ad76ae44c4211d28694e91ec62bddc1
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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Merge changes from topic "ADD_DELAY_IN_POLLING_SCMI" into integration

* changes:
fix(scmi): induce a delay in monitoring SCMI channel status
feat(css): initialise generic timer early in the boot

Merge changes from topic "stm32mp2-usb" into integration

* changes:
feat(stm32mp2): add STM32MP_USB_PROGRAMMER compilation
refactor(st): move macros to common folder
refactor(stm32mp1): remove

Merge changes from topic "stm32mp2-usb" into integration

* changes:
feat(stm32mp2): add STM32MP_USB_PROGRAMMER compilation
refactor(st): move macros to common folder
refactor(stm32mp1): remove unused macros
fix(usb): add missing include

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Merge changes I0e012f3f,I14ad16e8 into integration

* changes:
fix(rss): fix bound check during protocol selection
fix(mhuv2): provide only the usable size of memory

Merge changes from topic "od/sme" into integration

* changes:
fix(fvp): permit enabling SME for SPD=spmd
feat(spmd): pass SMCCCv1.3 SVE hint to lower EL

refactor(gicv3): introducing is_valid_interrupt, a new helper utility

In gicv3_main.c the function is_sgi_ppi() returns true when its
sgi/ppi or false when the interrupt number matches an spi interr

refactor(gicv3): introducing is_valid_interrupt, a new helper utility

In gicv3_main.c the function is_sgi_ppi() returns true when its
sgi/ppi or false when the interrupt number matches an spi interrupt.
Introducing a new API is_valid_interrupt() which validates if
an interrupt number matches SGI/PPI or SPI as a valid interrupt,
any other interrupt number is considered invalid and panics.

Change-Id: Idce8f5432a94c8d300b9408cf5b2502c60e13318
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(fvp): permit enabling SME for SPD=spmd

Essentially revert [1] to permit specifying SME support along with
SPD=spmd on FVP platform.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmwar

fix(fvp): permit enabling SME for SPD=spmd

Essentially revert [1] to permit specifying SME support along with
SPD=spmd on FVP platform.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/20764

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Iab15d5a4c966b9f5b265ccde6711765e242abeaa

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feat(spmd): pass SMCCCv1.3 SVE hint to lower EL

A normal world caller can emit an SMC with the SVE hint bit set such
that the callee can perform an optimization by omitting to save/restore
the SVE c

feat(spmd): pass SMCCCv1.3 SVE hint to lower EL

A normal world caller can emit an SMC with the SVE hint bit set such
that the callee can perform an optimization by omitting to save/restore
the SVE context. Update the SPMD to pass this information to the SPMC
when set by the caller in the SMC flags parameter.
For now, restrict this behavior to the SPMC living at S-EL2.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Icf46eb8a391dd3ddd2ee6aff8581a2f1c8a1c274

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