1 /* 2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARCH_HELPERS_H 8 #define ARCH_HELPERS_H 9 10 #include <cdefs.h> 11 #include <stdbool.h> 12 #include <stdint.h> 13 #include <string.h> 14 15 #include <arch.h> 16 17 /********************************************************************** 18 * Macros which create inline functions to read or write CPU system 19 * registers 20 *********************************************************************/ 21 22 #define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \ 23 static inline u_register_t read_ ## _name(void) \ 24 { \ 25 u_register_t v; \ 26 __asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \ 27 return v; \ 28 } 29 30 #define _DEFINE_SYSREG_READ_FUNC_NV(_name, _reg_name) \ 31 static inline u_register_t read_ ## _name(void) \ 32 { \ 33 u_register_t v; \ 34 __asm__ ("mrs %0, " #_reg_name : "=r" (v)); \ 35 return v; \ 36 } 37 38 #define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \ 39 static inline void write_ ## _name(u_register_t v) \ 40 { \ 41 __asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \ 42 } 43 44 #define SYSREG_WRITE_CONST(reg_name, v) \ 45 __asm__ volatile ("msr " #reg_name ", %0" : : "i" (v)) 46 47 /* Define read function for system register */ 48 #define DEFINE_SYSREG_READ_FUNC(_name) \ 49 _DEFINE_SYSREG_READ_FUNC(_name, _name) 50 51 /* Define read & write function for system register */ 52 #define DEFINE_SYSREG_RW_FUNCS(_name) \ 53 _DEFINE_SYSREG_READ_FUNC(_name, _name) \ 54 _DEFINE_SYSREG_WRITE_FUNC(_name, _name) 55 56 /* Define read & write function for renamed system register */ 57 #define DEFINE_RENAME_SYSREG_RW_FUNCS(_name, _reg_name) \ 58 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \ 59 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) 60 61 /* Define read function for renamed system register */ 62 #define DEFINE_RENAME_SYSREG_READ_FUNC(_name, _reg_name) \ 63 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) 64 65 /* Define write function for renamed system register */ 66 #define DEFINE_RENAME_SYSREG_WRITE_FUNC(_name, _reg_name) \ 67 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) 68 69 /* Define read function for ID register (w/o volatile qualifier) */ 70 #define DEFINE_IDREG_READ_FUNC(_name) \ 71 _DEFINE_SYSREG_READ_FUNC_NV(_name, _name) 72 73 /* Define read function for renamed ID register (w/o volatile qualifier) */ 74 #define DEFINE_RENAME_IDREG_READ_FUNC(_name, _reg_name) \ 75 _DEFINE_SYSREG_READ_FUNC_NV(_name, _reg_name) 76 77 /********************************************************************** 78 * Macros to create inline functions for system instructions 79 *********************************************************************/ 80 81 /* Define function for simple system instruction */ 82 #define DEFINE_SYSOP_FUNC(_op) \ 83 static inline void _op(void) \ 84 { \ 85 __asm__ (#_op); \ 86 } 87 88 /* Define function for system instruction with register parameter */ 89 #define DEFINE_SYSOP_PARAM_FUNC(_op) \ 90 static inline void _op(uint64_t v) \ 91 { \ 92 __asm__ (#_op " %0" : : "r" (v)); \ 93 } 94 95 /* Define function for system instruction with type specifier */ 96 #define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \ 97 static inline void _op ## _type(void) \ 98 { \ 99 __asm__ (#_op " " #_type : : : "memory"); \ 100 } 101 102 /* Define function for system instruction with register parameter */ 103 #define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \ 104 static inline void _op ## _type(uint64_t v) \ 105 { \ 106 __asm__ (#_op " " #_type ", %0" : : "r" (v)); \ 107 } 108 109 /******************************************************************************* 110 * TLB maintenance accessor prototypes 111 ******************************************************************************/ 112 113 #if ERRATA_A57_813419 || ERRATA_A76_1286807 114 /* 115 * Define function for TLBI instruction with type specifier that implements 116 * the workaround for errata 813419 of Cortex-A57 or errata 1286807 of 117 * Cortex-A76. 118 */ 119 #define DEFINE_TLBIOP_ERRATA_TYPE_FUNC(_type)\ 120 static inline void tlbi ## _type(void) \ 121 { \ 122 __asm__("tlbi " #_type "\n" \ 123 "dsb ish\n" \ 124 "tlbi " #_type); \ 125 } 126 127 /* 128 * Define function for TLBI instruction with register parameter that implements 129 * the workaround for errata 813419 of Cortex-A57 or errata 1286807 of 130 * Cortex-A76. 131 */ 132 #define DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(_type) \ 133 static inline void tlbi ## _type(uint64_t v) \ 134 { \ 135 __asm__("tlbi " #_type ", %0\n" \ 136 "dsb ish\n" \ 137 "tlbi " #_type ", %0" : : "r" (v)); \ 138 } 139 #endif /* ERRATA_A57_813419 */ 140 141 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 142 /* 143 * Define function for DC instruction with register parameter that enables 144 * the workaround for errata 819472, 824069 and 827319 of Cortex-A53. 145 */ 146 #define DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(_name, _type) \ 147 static inline void dc ## _name(uint64_t v) \ 148 { \ 149 __asm__("dc " #_type ", %0" : : "r" (v)); \ 150 } 151 #endif /* ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 */ 152 153 #if ERRATA_A57_813419 154 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1) 155 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is) 156 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2) 157 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is) 158 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3) 159 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3is) 160 DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1) 161 #elif ERRATA_A76_1286807 162 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle1) 163 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle1is) 164 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle2) 165 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle2is) 166 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3) 167 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3is) 168 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(vmalle1) 169 #else 170 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1) 171 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is) 172 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2) 173 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is) 174 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3) 175 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3is) 176 DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1) 177 #endif 178 179 #if ERRATA_A57_813419 180 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is) 181 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is) 182 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is) 183 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is) 184 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae3is) 185 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale3is) 186 #elif ERRATA_A76_1286807 187 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vaae1is) 188 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vaale1is) 189 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae2is) 190 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale2is) 191 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae3is) 192 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale3is) 193 #else 194 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is) 195 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is) 196 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is) 197 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is) 198 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae3is) 199 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale3is) 200 #endif 201 202 /******************************************************************************* 203 * Cache maintenance accessor prototypes 204 ******************************************************************************/ 205 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, isw) 206 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cisw) 207 #if ERRATA_A53_827319 208 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(csw, cisw) 209 #else 210 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, csw) 211 #endif 212 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 213 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvac, civac) 214 #else 215 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvac) 216 #endif 217 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, ivac) 218 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, civac) 219 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 220 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvau, civac) 221 #else 222 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvau) 223 #endif 224 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, zva) 225 226 /******************************************************************************* 227 * Address translation accessor prototypes 228 ******************************************************************************/ 229 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1r) 230 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1w) 231 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0r) 232 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0w) 233 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e1r) 234 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e2r) 235 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e3r) 236 237 /******************************************************************************* 238 * Strip Pointer Authentication Code 239 ******************************************************************************/ 240 DEFINE_SYSOP_PARAM_FUNC(xpaci) 241 242 void flush_dcache_range(uintptr_t addr, size_t size); 243 void flush_dcache_to_popa_range(uintptr_t addr, size_t size); 244 void flush_dcache_to_popa_range_mte2(uintptr_t addr, size_t size); 245 void clean_dcache_range(uintptr_t addr, size_t size); 246 void inv_dcache_range(uintptr_t addr, size_t size); 247 bool is_dcache_enabled(void); 248 249 void dcsw_op_louis(u_register_t op_type); 250 void dcsw_op_all(u_register_t op_type); 251 252 void disable_mmu_el1(void); 253 void disable_mmu_el3(void); 254 void disable_mpu_el2(void); 255 void disable_mmu_icache_el1(void); 256 void disable_mmu_icache_el3(void); 257 void disable_mpu_icache_el2(void); 258 259 /******************************************************************************* 260 * Misc. accessor prototypes 261 ******************************************************************************/ 262 263 #define write_daifclr(val) SYSREG_WRITE_CONST(daifclr, val) 264 #define write_daifset(val) SYSREG_WRITE_CONST(daifset, val) 265 266 DEFINE_SYSREG_RW_FUNCS(par_el1) 267 DEFINE_IDREG_READ_FUNC(id_pfr1_el1) 268 DEFINE_IDREG_READ_FUNC(id_aa64isar0_el1) 269 DEFINE_IDREG_READ_FUNC(id_aa64isar1_el1) 270 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64isar2_el1, ID_AA64ISAR2_EL1) 271 DEFINE_IDREG_READ_FUNC(id_aa64pfr0_el1) 272 DEFINE_IDREG_READ_FUNC(id_aa64pfr1_el1) 273 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64pfr2_el1, ID_AA64PFR2_EL1) 274 DEFINE_IDREG_READ_FUNC(id_aa64dfr0_el1) 275 DEFINE_IDREG_READ_FUNC(id_afr0_el1) 276 DEFINE_SYSREG_READ_FUNC(CurrentEl) 277 DEFINE_SYSREG_READ_FUNC(ctr_el0) 278 DEFINE_SYSREG_RW_FUNCS(daif) 279 DEFINE_SYSREG_RW_FUNCS(spsr_el1) 280 DEFINE_SYSREG_RW_FUNCS(spsr_el2) 281 DEFINE_SYSREG_RW_FUNCS(spsr_el3) 282 DEFINE_SYSREG_RW_FUNCS(elr_el1) 283 DEFINE_SYSREG_RW_FUNCS(elr_el2) 284 DEFINE_SYSREG_RW_FUNCS(elr_el3) 285 DEFINE_SYSREG_RW_FUNCS(mdccsr_el0) 286 DEFINE_SYSREG_RW_FUNCS(dbgdtrrx_el0) 287 DEFINE_SYSREG_RW_FUNCS(dbgdtrtx_el0) 288 DEFINE_SYSREG_RW_FUNCS(sp_el1) 289 DEFINE_SYSREG_RW_FUNCS(sp_el2) 290 291 DEFINE_SYSOP_FUNC(wfi) 292 DEFINE_SYSOP_FUNC(wfe) 293 DEFINE_SYSOP_FUNC(sev) 294 DEFINE_SYSOP_TYPE_FUNC(dsb, sy) 295 DEFINE_SYSOP_TYPE_FUNC(dmb, sy) 296 DEFINE_SYSOP_TYPE_FUNC(dmb, st) 297 DEFINE_SYSOP_TYPE_FUNC(dmb, ld) 298 DEFINE_SYSOP_TYPE_FUNC(dsb, ish) 299 DEFINE_SYSOP_TYPE_FUNC(dsb, osh) 300 DEFINE_SYSOP_TYPE_FUNC(dsb, nsh) 301 DEFINE_SYSOP_TYPE_FUNC(dsb, ishst) 302 DEFINE_SYSOP_TYPE_FUNC(dsb, oshst) 303 DEFINE_SYSOP_TYPE_FUNC(dmb, oshld) 304 DEFINE_SYSOP_TYPE_FUNC(dmb, oshst) 305 DEFINE_SYSOP_TYPE_FUNC(dmb, osh) 306 DEFINE_SYSOP_TYPE_FUNC(dmb, nshld) 307 DEFINE_SYSOP_TYPE_FUNC(dmb, nshst) 308 DEFINE_SYSOP_TYPE_FUNC(dmb, nsh) 309 DEFINE_SYSOP_TYPE_FUNC(dmb, ishld) 310 DEFINE_SYSOP_TYPE_FUNC(dmb, ishst) 311 DEFINE_SYSOP_TYPE_FUNC(dmb, ish) 312 DEFINE_SYSOP_FUNC(isb) 313 314 static inline void enable_irq(void) 315 { 316 /* 317 * The compiler memory barrier will prevent the compiler from 318 * scheduling non-volatile memory access after the write to the 319 * register. 320 * 321 * This could happen if some initialization code issues non-volatile 322 * accesses to an area used by an interrupt handler, in the assumption 323 * that it is safe as the interrupts are disabled at the time it does 324 * that (according to program order). However, non-volatile accesses 325 * are not necessarily in program order relatively with volatile inline 326 * assembly statements (and volatile accesses). 327 */ 328 COMPILER_BARRIER(); 329 write_daifclr(DAIF_IRQ_BIT); 330 isb(); 331 } 332 333 static inline void enable_fiq(void) 334 { 335 COMPILER_BARRIER(); 336 write_daifclr(DAIF_FIQ_BIT); 337 isb(); 338 } 339 340 static inline void enable_serror(void) 341 { 342 COMPILER_BARRIER(); 343 write_daifclr(DAIF_ABT_BIT); 344 isb(); 345 } 346 347 static inline void enable_debug_exceptions(void) 348 { 349 COMPILER_BARRIER(); 350 write_daifclr(DAIF_DBG_BIT); 351 isb(); 352 } 353 354 static inline void disable_irq(void) 355 { 356 COMPILER_BARRIER(); 357 write_daifset(DAIF_IRQ_BIT); 358 isb(); 359 } 360 361 static inline void disable_fiq(void) 362 { 363 COMPILER_BARRIER(); 364 write_daifset(DAIF_FIQ_BIT); 365 isb(); 366 } 367 368 static inline void disable_serror(void) 369 { 370 COMPILER_BARRIER(); 371 write_daifset(DAIF_ABT_BIT); 372 isb(); 373 } 374 375 static inline void disable_debug_exceptions(void) 376 { 377 COMPILER_BARRIER(); 378 write_daifset(DAIF_DBG_BIT); 379 isb(); 380 } 381 382 void __dead2 smc(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, 383 uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7); 384 385 /******************************************************************************* 386 * System register accessor prototypes 387 ******************************************************************************/ 388 DEFINE_IDREG_READ_FUNC(midr_el1) 389 DEFINE_SYSREG_READ_FUNC(mpidr_el1) 390 DEFINE_IDREG_READ_FUNC(id_aa64mmfr0_el1) 391 DEFINE_IDREG_READ_FUNC(id_aa64mmfr1_el1) 392 393 DEFINE_SYSREG_RW_FUNCS(scr_el3) 394 DEFINE_SYSREG_RW_FUNCS(hcr_el2) 395 396 DEFINE_SYSREG_RW_FUNCS(vbar_el1) 397 DEFINE_SYSREG_RW_FUNCS(vbar_el2) 398 DEFINE_SYSREG_RW_FUNCS(vbar_el3) 399 400 DEFINE_SYSREG_RW_FUNCS(sctlr_el1) 401 DEFINE_SYSREG_RW_FUNCS(sctlr_el2) 402 DEFINE_SYSREG_RW_FUNCS(sctlr_el3) 403 404 DEFINE_SYSREG_RW_FUNCS(actlr_el1) 405 DEFINE_SYSREG_RW_FUNCS(actlr_el2) 406 DEFINE_SYSREG_RW_FUNCS(actlr_el3) 407 408 DEFINE_SYSREG_RW_FUNCS(esr_el1) 409 DEFINE_SYSREG_RW_FUNCS(esr_el2) 410 DEFINE_SYSREG_RW_FUNCS(esr_el3) 411 412 DEFINE_SYSREG_RW_FUNCS(afsr0_el1) 413 DEFINE_SYSREG_RW_FUNCS(afsr0_el2) 414 DEFINE_SYSREG_RW_FUNCS(afsr0_el3) 415 416 DEFINE_SYSREG_RW_FUNCS(afsr1_el1) 417 DEFINE_SYSREG_RW_FUNCS(afsr1_el2) 418 DEFINE_SYSREG_RW_FUNCS(afsr1_el3) 419 420 DEFINE_SYSREG_RW_FUNCS(far_el1) 421 DEFINE_SYSREG_RW_FUNCS(far_el2) 422 DEFINE_SYSREG_RW_FUNCS(far_el3) 423 424 DEFINE_SYSREG_RW_FUNCS(mair_el1) 425 DEFINE_SYSREG_RW_FUNCS(mair_el2) 426 DEFINE_SYSREG_RW_FUNCS(mair_el3) 427 428 DEFINE_SYSREG_RW_FUNCS(amair_el1) 429 DEFINE_SYSREG_RW_FUNCS(amair_el2) 430 DEFINE_SYSREG_RW_FUNCS(amair_el3) 431 432 DEFINE_SYSREG_READ_FUNC(rvbar_el1) 433 DEFINE_SYSREG_READ_FUNC(rvbar_el2) 434 DEFINE_SYSREG_READ_FUNC(rvbar_el3) 435 436 DEFINE_SYSREG_RW_FUNCS(rmr_el1) 437 DEFINE_SYSREG_RW_FUNCS(rmr_el2) 438 DEFINE_SYSREG_RW_FUNCS(rmr_el3) 439 440 DEFINE_SYSREG_RW_FUNCS(tcr_el1) 441 DEFINE_SYSREG_RW_FUNCS(tcr_el2) 442 DEFINE_SYSREG_RW_FUNCS(tcr_el3) 443 444 DEFINE_SYSREG_RW_FUNCS(ttbr0_el1) 445 DEFINE_SYSREG_RW_FUNCS(ttbr0_el2) 446 DEFINE_SYSREG_RW_FUNCS(ttbr0_el3) 447 448 DEFINE_SYSREG_RW_FUNCS(ttbr1_el1) 449 450 DEFINE_SYSREG_RW_FUNCS(vttbr_el2) 451 452 DEFINE_SYSREG_RW_FUNCS(cptr_el2) 453 DEFINE_SYSREG_RW_FUNCS(cptr_el3) 454 455 DEFINE_SYSREG_RW_FUNCS(cpacr_el1) 456 DEFINE_SYSREG_RW_FUNCS(cntfrq_el0) 457 DEFINE_SYSREG_RW_FUNCS(cnthp_ctl_el2) 458 DEFINE_SYSREG_RW_FUNCS(cnthp_tval_el2) 459 DEFINE_SYSREG_RW_FUNCS(cnthp_cval_el2) 460 DEFINE_SYSREG_RW_FUNCS(cntps_ctl_el1) 461 DEFINE_SYSREG_RW_FUNCS(cntps_tval_el1) 462 DEFINE_SYSREG_RW_FUNCS(cntps_cval_el1) 463 DEFINE_SYSREG_RW_FUNCS(cntp_ctl_el0) 464 DEFINE_SYSREG_RW_FUNCS(cntp_tval_el0) 465 DEFINE_SYSREG_RW_FUNCS(cntp_cval_el0) 466 DEFINE_SYSREG_READ_FUNC(cntpct_el0) 467 DEFINE_SYSREG_RW_FUNCS(cnthctl_el2) 468 469 DEFINE_SYSREG_RW_FUNCS(vtcr_el2) 470 471 #define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \ 472 CNTP_CTL_ENABLE_MASK) 473 #define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \ 474 CNTP_CTL_IMASK_MASK) 475 #define get_cntp_ctl_istatus(x) (((x) >> CNTP_CTL_ISTATUS_SHIFT) & \ 476 CNTP_CTL_ISTATUS_MASK) 477 478 #define set_cntp_ctl_enable(x) ((x) |= (U(1) << CNTP_CTL_ENABLE_SHIFT)) 479 #define set_cntp_ctl_imask(x) ((x) |= (U(1) << CNTP_CTL_IMASK_SHIFT)) 480 481 #define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT)) 482 #define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT)) 483 484 DEFINE_SYSREG_RW_FUNCS(tpidr_el3) 485 486 DEFINE_SYSREG_RW_FUNCS(cntvoff_el2) 487 488 DEFINE_SYSREG_RW_FUNCS(vpidr_el2) 489 DEFINE_SYSREG_RW_FUNCS(vmpidr_el2) 490 491 DEFINE_SYSREG_RW_FUNCS(hacr_el2) 492 DEFINE_SYSREG_RW_FUNCS(hpfar_el2) 493 DEFINE_SYSREG_RW_FUNCS(tpidr_el2) 494 DEFINE_SYSREG_RW_FUNCS(dbgvcr32_el2) 495 DEFINE_RENAME_SYSREG_RW_FUNCS(ich_hcr_el2, ICH_HCR_EL2) 496 DEFINE_RENAME_SYSREG_RW_FUNCS(ich_vmcr_el2, ICH_VMCR_EL2) 497 498 DEFINE_SYSREG_READ_FUNC(isr_el1) 499 500 DEFINE_SYSREG_RW_FUNCS(mdcr_el2) 501 DEFINE_SYSREG_RW_FUNCS(mdcr_el3) 502 DEFINE_SYSREG_RW_FUNCS(hstr_el2) 503 DEFINE_SYSREG_RW_FUNCS(pmcr_el0) 504 505 /* GICv3 System Registers */ 506 507 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1) 508 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2) 509 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el3, ICC_SRE_EL3) 510 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_pmr_el1, ICC_PMR_EL1) 511 DEFINE_RENAME_SYSREG_READ_FUNC(icc_rpr_el1, ICC_RPR_EL1) 512 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el3, ICC_IGRPEN1_EL3) 513 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el1, ICC_IGRPEN1_EL1) 514 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0_EL1) 515 DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir0_el1, ICC_HPPIR0_EL1) 516 DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir1_el1, ICC_HPPIR1_EL1) 517 DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar0_el1, ICC_IAR0_EL1) 518 DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar1_el1, ICC_IAR1_EL1) 519 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir0_el1, ICC_EOIR0_EL1) 520 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1) 521 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_sgi0r_el1, ICC_SGI0R_EL1) 522 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sgi1r, ICC_SGI1R) 523 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_asgi1r, ICC_ASGI1R) 524 525 DEFINE_RENAME_SYSREG_READ_FUNC(amcfgr_el0, AMCFGR_EL0) 526 DEFINE_RENAME_SYSREG_READ_FUNC(amcgcr_el0, AMCGCR_EL0) 527 DEFINE_RENAME_SYSREG_READ_FUNC(amcg1idr_el0, AMCG1IDR_EL0) 528 DEFINE_RENAME_SYSREG_RW_FUNCS(amcr_el0, AMCR_EL0) 529 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr0_el0, AMCNTENCLR0_EL0) 530 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset0_el0, AMCNTENSET0_EL0) 531 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr1_el0, AMCNTENCLR1_EL0) 532 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset1_el0, AMCNTENSET1_EL0) 533 534 DEFINE_RENAME_SYSREG_RW_FUNCS(pmblimitr_el1, PMBLIMITR_EL1) 535 536 DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el3, ZCR_EL3) 537 DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el2, ZCR_EL2) 538 539 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64smfr0_el1, ID_AA64SMFR0_EL1) 540 DEFINE_RENAME_SYSREG_RW_FUNCS(smcr_el3, SMCR_EL3) 541 542 DEFINE_RENAME_SYSREG_READ_FUNC(erridr_el1, ERRIDR_EL1) 543 DEFINE_RENAME_SYSREG_WRITE_FUNC(errselr_el1, ERRSELR_EL1) 544 545 DEFINE_RENAME_SYSREG_READ_FUNC(erxfr_el1, ERXFR_EL1) 546 DEFINE_RENAME_SYSREG_RW_FUNCS(erxctlr_el1, ERXCTLR_EL1) 547 DEFINE_RENAME_SYSREG_RW_FUNCS(erxstatus_el1, ERXSTATUS_EL1) 548 DEFINE_RENAME_SYSREG_READ_FUNC(erxaddr_el1, ERXADDR_EL1) 549 DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc0_el1, ERXMISC0_EL1) 550 DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc1_el1, ERXMISC1_EL1) 551 552 DEFINE_RENAME_SYSREG_RW_FUNCS(scxtnum_el2, SCXTNUM_EL2) 553 554 /* Armv8.1 VHE Registers */ 555 DEFINE_RENAME_SYSREG_RW_FUNCS(contextidr_el2, CONTEXTIDR_EL2) 556 DEFINE_RENAME_SYSREG_RW_FUNCS(ttbr1_el2, TTBR1_EL2) 557 558 /* Armv8.2 ID Registers */ 559 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1) 560 561 /* Armv8.2 RAS Registers */ 562 DEFINE_RENAME_SYSREG_RW_FUNCS(vdisr_el2, VDISR_EL2) 563 DEFINE_RENAME_SYSREG_RW_FUNCS(vsesr_el2, VSESR_EL2) 564 565 /* Armv8.2 MPAM Registers */ 566 DEFINE_RENAME_SYSREG_READ_FUNC(mpamidr_el1, MPAMIDR_EL1) 567 DEFINE_RENAME_SYSREG_RW_FUNCS(mpam3_el3, MPAM3_EL3) 568 DEFINE_RENAME_SYSREG_RW_FUNCS(mpam2_el2, MPAM2_EL2) 569 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamhcr_el2, MPAMHCR_EL2) 570 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm0_el2, MPAMVPM0_EL2) 571 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm1_el2, MPAMVPM1_EL2) 572 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm2_el2, MPAMVPM2_EL2) 573 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm3_el2, MPAMVPM3_EL2) 574 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm4_el2, MPAMVPM4_EL2) 575 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm5_el2, MPAMVPM5_EL2) 576 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm6_el2, MPAMVPM6_EL2) 577 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm7_el2, MPAMVPM7_EL2) 578 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpmv_el2, MPAMVPMV_EL2) 579 580 /* Armv8.3 Pointer Authentication Registers */ 581 DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeyhi_el1, APIAKeyHi_EL1) 582 DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeylo_el1, APIAKeyLo_EL1) 583 584 /* Armv8.4 Data Independent Timing Register */ 585 DEFINE_RENAME_SYSREG_RW_FUNCS(dit, DIT) 586 587 /* Armv8.4 FEAT_TRF Register */ 588 DEFINE_RENAME_SYSREG_RW_FUNCS(trfcr_el2, TRFCR_EL2) 589 DEFINE_RENAME_SYSREG_RW_FUNCS(vncr_el2, VNCR_EL2) 590 591 /* Armv8.5 MTE Registers */ 592 DEFINE_RENAME_SYSREG_RW_FUNCS(tfsre0_el1, TFSRE0_EL1) 593 DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1) 594 DEFINE_RENAME_SYSREG_RW_FUNCS(rgsr_el1, RGSR_EL1) 595 DEFINE_RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1) 596 DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el2, TFSR_EL2) 597 598 /* Armv8.5 FEAT_RNG Registers */ 599 DEFINE_RENAME_SYSREG_READ_FUNC(rndr, RNDR) 600 DEFINE_RENAME_SYSREG_READ_FUNC(rndrrs, RNDRRS) 601 602 /* Armv8.6 FEAT_FGT Registers */ 603 DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgrtr_el2, HDFGRTR_EL2) 604 DEFINE_RENAME_SYSREG_RW_FUNCS(hafgrtr_el2, HAFGRTR_EL2) 605 DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgwtr_el2, HDFGWTR_EL2) 606 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgitr_el2, HFGITR_EL2) 607 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgrtr_el2, HFGRTR_EL2) 608 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgwtr_el2, HFGWTR_EL2) 609 610 /* ARMv8.6 FEAT_ECV Register */ 611 DEFINE_RENAME_SYSREG_RW_FUNCS(cntpoff_el2, CNTPOFF_EL2) 612 613 /* FEAT_HCX Register */ 614 DEFINE_RENAME_SYSREG_RW_FUNCS(hcrx_el2, HCRX_EL2) 615 616 /* Armv8.9 system registers */ 617 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64mmfr3_el1, ID_AA64MMFR3_EL1) 618 619 /* FEAT_TCR2 Register */ 620 DEFINE_RENAME_SYSREG_RW_FUNCS(tcr2_el2, TCR2_EL2) 621 622 /* FEAT_SxPIE Registers */ 623 DEFINE_RENAME_SYSREG_RW_FUNCS(pire0_el2, PIRE0_EL2) 624 DEFINE_RENAME_SYSREG_RW_FUNCS(pir_el2, PIR_EL2) 625 DEFINE_RENAME_SYSREG_RW_FUNCS(s2pir_el2, S2PIR_EL2) 626 627 /* FEAT_SxPOE Registers */ 628 DEFINE_RENAME_SYSREG_RW_FUNCS(por_el2, POR_EL2) 629 630 /* FEAT_GCS Registers */ 631 DEFINE_RENAME_SYSREG_RW_FUNCS(gcscr_el2, GCSCR_EL2) 632 DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el2, GCSPR_EL2) 633 634 /* DynamIQ Shared Unit power management */ 635 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrdn_el1, CLUSTERPWRDN_EL1) 636 637 /* CPU Power/Performance Management registers */ 638 DEFINE_RENAME_SYSREG_RW_FUNCS(cpuppmcr_el3, CPUPPMCR_EL3) 639 DEFINE_RENAME_SYSREG_RW_FUNCS(cpumpmmcr_el3, CPUMPMMCR_EL3) 640 641 /* Armv9.2 RME Registers */ 642 DEFINE_RENAME_SYSREG_RW_FUNCS(gptbr_el3, GPTBR_EL3) 643 DEFINE_RENAME_SYSREG_RW_FUNCS(gpccr_el3, GPCCR_EL3) 644 645 #define IS_IN_EL(x) \ 646 (GET_EL(read_CurrentEl()) == MODE_EL##x) 647 648 #define IS_IN_EL1() IS_IN_EL(1) 649 #define IS_IN_EL2() IS_IN_EL(2) 650 #define IS_IN_EL3() IS_IN_EL(3) 651 652 static inline unsigned int get_current_el(void) 653 { 654 return GET_EL(read_CurrentEl()); 655 } 656 657 static inline unsigned int get_current_el_maybe_constant(void) 658 { 659 #if defined(IMAGE_AT_EL1) 660 return 1; 661 #elif defined(IMAGE_AT_EL2) 662 return 2; /* no use-case in TF-A */ 663 #elif defined(IMAGE_AT_EL3) 664 return 3; 665 #else 666 /* 667 * If we do not know which exception level this is being built for 668 * (e.g. built for library), fall back to run-time detection. 669 */ 670 return get_current_el(); 671 #endif 672 } 673 674 /* 675 * Check if an EL is implemented from AA64PFR0 register fields. 676 */ 677 static inline uint64_t el_implemented(unsigned int el) 678 { 679 if (el > 3U) { 680 return EL_IMPL_NONE; 681 } else { 682 unsigned int shift = ID_AA64PFR0_EL1_SHIFT * el; 683 684 return (read_id_aa64pfr0_el1() >> shift) & ID_AA64PFR0_ELX_MASK; 685 } 686 } 687 688 /* 689 * TLBIPAALLOS instruction 690 * (TLB Inivalidate GPT Information by PA, 691 * All Entries, Outer Shareable) 692 */ 693 static inline void tlbipaallos(void) 694 { 695 __asm__("SYS #6,c8,c1,#4"); 696 } 697 698 /* 699 * Invalidate TLBs of GPT entries by Physical address, last level. 700 * 701 * @pa: the starting address for the range 702 * of invalidation 703 * @size: size of the range of invalidation 704 */ 705 void gpt_tlbi_by_pa_ll(uint64_t pa, size_t size); 706 707 708 /* Previously defined accessor functions with incomplete register names */ 709 710 #define read_current_el() read_CurrentEl() 711 712 #define dsb() dsbsy() 713 714 #define read_midr() read_midr_el1() 715 716 #define read_mpidr() read_mpidr_el1() 717 718 #define read_scr() read_scr_el3() 719 #define write_scr(_v) write_scr_el3(_v) 720 721 #define read_hcr() read_hcr_el2() 722 #define write_hcr(_v) write_hcr_el2(_v) 723 724 #define read_cpacr() read_cpacr_el1() 725 #define write_cpacr(_v) write_cpacr_el1(_v) 726 727 #define read_clusterpwrdn() read_clusterpwrdn_el1() 728 #define write_clusterpwrdn(_v) write_clusterpwrdn_el1(_v) 729 730 #if ERRATA_SPECULATIVE_AT 731 /* 732 * Assuming SCTLR.M bit is already enabled 733 * 1. Enable page table walk by clearing TCR_EL1.EPDx bits 734 * 2. Execute AT instruction for lower EL1/0 735 * 3. Disable page table walk by setting TCR_EL1.EPDx bits 736 */ 737 #define AT(_at_inst, _va) \ 738 { \ 739 assert((read_sctlr_el1() & SCTLR_M_BIT) != 0ULL); \ 740 write_tcr_el1(read_tcr_el1() & ~(TCR_EPD0_BIT | TCR_EPD1_BIT)); \ 741 isb(); \ 742 _at_inst(_va); \ 743 write_tcr_el1(read_tcr_el1() | (TCR_EPD0_BIT | TCR_EPD1_BIT)); \ 744 isb(); \ 745 } 746 #else 747 #define AT(_at_inst, _va) _at_inst(_va) 748 #endif 749 750 #endif /* ARCH_HELPERS_H */ 751