fix(cpus): workaround for Cortex-X3 erratum 2372204

Cortex-X3 erratum 2372204 is a Cat B erratum that applies to revisions
r0p0 and r1p0. It is fixed in r1p1.

The workaround is to set bit[40] of CP

fix(cpus): workaround for Cortex-X3 erratum 2372204

Cortex-X3 erratum 2372204 is a Cat B erratum that applies to revisions
r0p0 and r1p0. It is fixed in r1p1.

The workaround is to set bit[40] of CPUACTLR2_EL1 to disable folding
of demand requests into older prefetches with L2 miss requests
outstanding.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN2055130/latest

Change-Id: Iad28f8625c84186fbd8049406d139d4f15c6e069
Signed-off-by: Bipin Ravi <biprav01@u203721.austin.arm.com>

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Merge changes I6ac59693,Ib0e4e5cf into integration

* changes:
refactor(tc): reorder config variable defines
refactor(tc): move DTB to start of DRAM

Merge changes from topic "mp/undef_injection" into integration

* changes:
feat(el3-runtime): introduce UNDEF injection to lower EL
feat(cpufeat): added few helper functions

feat(el3-runtime): introduce UNDEF injection to lower EL

For a feature to be used at lower ELs, EL3 generally needs to disable
the trap so that lower ELs can access the system registers associated
w

feat(el3-runtime): introduce UNDEF injection to lower EL

For a feature to be used at lower ELs, EL3 generally needs to disable
the trap so that lower ELs can access the system registers associated
with the feature. Lower ELs generally check ID registers to dynamically
detect if a feature is present (in HW) or not while EL3 Firmware relies
statically on feature build macros to enable a feature.

If a lower EL accesses a system register for a feature that EL3 FW is
unaware of, EL3 traps the access and panics. This happens mostly with
EL2 but sometimes VMs can also cause EL3 panic.

To provide platforms with capability to mitigate this problem, UNDEF
injection support has been introduced which injects a synchronous
exception into the lower EL which is supposed to handle the
synchronous exception.

The current support is only provided for aarch64.

The implementation does the following on encountering sys reg trap

- Get the target EL, which can be either EL2 or EL1
- Update ELR_ELx with ELR_EL3, so that after UNDEF handling in lower EL
control returns to original location.
- ESR_ELx with EC_UNKNOWN
- Update ELR_EL3 with vector address of sync exception handler with
following possible causes
- Current EL with SP0
- Current EL with SPx
- Lower EL using AArch64
- Re-create SPSR_EL3 which will be used to generate PSTATE at ERET

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I1b7bf6c043ce7aec1ee4fc1121c389b490b7bfb7

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Merge "fix(gpt): use DC CIGDPAPA when MTE2 is implemented" into integration

Merge changes from topic "part_crc" into integration

* changes:
feat(gpt): validate CRC of GPT partition entries
refactor(gpt): return header instead of part_lba

feat(cpufeat): added few helper functions

Following utility functions/bit definitions done
- Write a helper function to return the presence of following features
- FEAT_UAO
- FEAT_EBEP

feat(cpufeat): added few helper functions

Following utility functions/bit definitions done
- Write a helper function to return the presence of following features
- FEAT_UAO
- FEAT_EBEP
- FEAT_SEBEP
- FEAT_SSBS
- FEAT_NMI
- FEAT_PAN
- Add definition of some missing bits of SPSR.
- Add GCSCR_EL1 register encoding and accessor function.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ifcead0dd8e3b32096e4ab810dde5d582a889785a

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build(npm): update Node.js and all packages

This change updates the Node Version Manager version file to the latest
long-term release version of Node.js, v20.11.1, and the Node.js Package
Manager pa

build(npm): update Node.js and all packages

This change updates the Node Version Manager version file to the latest
long-term release version of Node.js, v20.11.1, and the Node.js Package
Manager package file to require Node.js version v20 or later.

Additionally, all Node.js modules have been updated, as some packages
required additional accommodations to be made compatible with this
version of Node.js.

As part of this, the `.commitlintrc.js` has been rewritten from CommonJS
to ECMAScript. There should be no impact on the behaviour of Commitlint,
but this was was a requirement to allow Commitlint to continue using it
for configuration.

Change-Id: I7043faabc516c58edda9e58848b0569e2158b271
Signed-off-by: Chris Kay <chris.kay@arm.com>

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feat(gpt): validate CRC of GPT partition entries

While loading partition entries, calculate CRC using tf_crc32() for each
entry to find the full CRC value of the partition entry array.

The start of

feat(gpt): validate CRC of GPT partition entries

While loading partition entries, calculate CRC using tf_crc32() for each
entry to find the full CRC value of the partition entry array.

The start of the GPT partition entry array is located at the LBA
indicated by the partition entry array LBA field in the GPT header. The
size of the partition entry array is indicated by the size of partition
entry multiplied by the number of partition entries.

Compare the calculated CRC with the partition entry array CRC in the GPT
header, error out if the values do not match.

Change-Id: I4bfed8cf903125c1ef3fac2f0f4c0fb87d63aa78
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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refactor(gpt): return header instead of part_lba

Alter the function parameter to pass the full GPT header to be filled
instead of the starting LBA of the array of partion entries to
load_partition_g

refactor(gpt): return header instead of part_lba

Alter the function parameter to pass the full GPT header to be filled
instead of the starting LBA of the array of partion entries to
load_partition_gpt()

Change-Id: Ib3dde62d5b9996e74157714634bea748bd3b55aa
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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Merge changes I1415e402,Ia92cc693,I7a42f72e,I6e75659e,I4c6136c5, ... into integration

* changes:
refactor(tc): correlate secure world addresses with platform_def
feat(tc): add memory node in the

Merge changes I1415e402,Ia92cc693,I7a42f72e,I6e75659e,I4c6136c5, ... into integration

* changes:
refactor(tc): correlate secure world addresses with platform_def
feat(tc): add memory node in the device tree
feat(tc): pass the DTB address to BL33 in R0
feat(tc): add arm_ffa node in dts
chore(tc): add dummy entropy to speed up the Linux boot
feat(tc): choose the DPU address and irq based on the target
feat(tc): add SCMI power domain and IOMMU toggles
refactor(tc): move the FVP RoS to a separate file
feat(tc): factor in FVP/FPGA differences
feat(tc): introduce an FPGA subvariant and TC3 CPUs
feat(tc): add TC3 platform definitions
refactor(tc): sanitise the device tree
feat(tc): add PMU entry
feat(tc): allow booting from DRAM
chore(tc): remove unused hdlcd
feat(tc): add firmware update secure partition
feat(tc): add spmc manifest with trusty sp
refactor(tc): unify all the spmc manifests
feat(arm): add trusty_sp_fw_config build option
fix(tc): do not enable MPMM and Aux AMU counters always
fix(tc): correct interrupts
feat(tc): interrupt numbers for `smmu_700`
feat(tc): enable gpu/dpu scmi power domain and also gpu perf domain

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Merge "fix(psa): fix static check failure" into integration

docs(maintainers): add the maintainers for imx8ulp

Add the maintainers for NXP i.MX8ULP.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ifc5f86ad6eb7288ef28765311fc3b1ff48031df5

docs(imx8ulp): add imx8ulp platform

Add i.MX8ULP platform introduction.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Idc16bcf5b23542f8a1f394a474309239ddcb9685

fix(imx8ulp): increase the mmap region num

the mmap region num is not enough for the mmap regions,
so increase it, increase the xlat_table num too.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Chang

fix(imx8ulp): increase the mmap region num

the mmap region num is not enough for the mmap regions,
so increase it, increase the xlat_table num too.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I2a2515b291e96cc12398a2c2c526351342811fff

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feat(imx8ulp): adjust the dram mapped region

below commit mapped 16 MB memory from the start of DRAM(0x80000000),
which may have conflict with the shared memory used by Trusty OS:
LF-8819: plat: i

feat(imx8ulp): adjust the dram mapped region

below commit mapped 16 MB memory from the start of DRAM(0x80000000),
which may have conflict with the shared memory used by Trusty OS:
LF-8819: plat: imx8ulp: ddrc switch auto low power and software interface

change the mapped memory to 'vdev0buffer' reserved memory (0x8ff00000)
to avoid memory conflict. This commit also bumps the XTLB tables
to avoid mapping failure.

Signed-off-by: Ji Luo <ji.luo@nxp.com>
Change-Id: I1a7af958af47e3fc9955d0a80d1649971e843eab

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feat(imx8ulp): ddrc switch auto low power and software interface

Enable switch between DDRC Auto low power and software/hardware
control modes DDRC Auto low-power mode is used when system is
active,

feat(imx8ulp): ddrc switch auto low power and software interface

Enable switch between DDRC Auto low power and software/hardware
control modes DDRC Auto low-power mode is used when system is
active, software/hardware control mode is used when going into
suspend. Enable switching between Auto mode and SW/HW mode in
enter/exit retention routines.

Set LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2 Max setting to allow
LPDDR_EN_CLKGATE reload LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2 to
exit retention mode

Signed-off-by: Pascal Mareau <pascal.mareau@nxp.com>
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Signed-off-by: Hongting Ting <hongting.dong@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I3c4b6f7bc6ca02649ff27cd3d9a0c50dab3a3ad0

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feat(imx8ulp): add some delay before cmc1 access

When resume from APD sleep mode, need to add a small delay
before accessing the CMC1 register.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-

feat(imx8ulp): add some delay before cmc1 access

When resume from APD sleep mode, need to add a small delay
before accessing the CMC1 register.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: Ic8acdf58a3bf82b1791e7ae7f173f8c94c56b49d

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feat(imx8ulp): add a flag check for the ddr status

for some user case, the ddr may need to be controlled
by RTD side to save power, when APD resume from low
power mode, it should wait ddr is ready f

feat(imx8ulp): add a flag check for the ddr status

for some user case, the ddr may need to be controlled
by RTD side to save power, when APD resume from low
power mode, it should wait ddr is ready for access.
currently we use a GPR in SIM_RTD_SEC as a flag to
indicate when the DDR is for access, non-zero value
means the DDR can be access from APD.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I6fb0cc17a040d803a597304620202423f646f294

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fix(imx8ulp): add sw workaround for csi/hotplug test hang

When doing CSI stress test after cpu hotplug, sometimes, system
will hang in CSI test. After some debug, we find that if slow
down the APD N

fix(imx8ulp): add sw workaround for csi/hotplug test hang

When doing CSI stress test after cpu hotplug, sometimes, system
will hang in CSI test. After some debug, we find that if slow
down the APD NIC frequency before power on the offline CPU,
the issue is gone. For now, just add such SW workaround.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: I39a49efc382fbebf46e1ff15c93d506bd5f6bec1

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feat(imx8ulp): adjust the voltage when sys dvfs enabled

When system level DVFS is enabled, voltage can be changed to
optimize the power consumption.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Revi

feat(imx8ulp): adjust the voltage when sys dvfs enabled

When system level DVFS is enabled, voltage can be changed to
optimize the power consumption.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: Idfa0e637402078f3daf6e7c4ea1abb9af7675494

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feat(imx8ulp): enable the DDR frequency scaling support

Enable the DDR frequency scaling support on i.MX8ULP.
Normally, the freq_index define is as below:

0: boot frequency;
1: low frequency(PLL

feat(imx8ulp): enable the DDR frequency scaling support

Enable the DDR frequency scaling support on i.MX8ULP.
Normally, the freq_index define is as below:

0: boot frequency;
1: low frequency(PLL bypassed);
2. high frequency(PLL ON).

Currently, DDR DFS only do frequency switching between
Low freq and high freq.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: I3acd8bdf75e2dd6dff645b9f597dcfc0a756c428

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fix(imx8ulp): fix suspend/resume issue when DBD owner is s400 only

After resume from APD power down, XRDC is initialized by S400 but
the PAC2 and MSC0-2 are not configured, so only DBD owner can acc

fix(imx8ulp): fix suspend/resume issue when DBD owner is s400 only

After resume from APD power down, XRDC is initialized by S400 but
the PAC2 and MSC0-2 are not configured, so only DBD owner can access
the resources.

We have to move GPIO restore after TFA XRDC reinit and configure
PDAC for PCC5 before enabling eDMA2 MP clock

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I82748de080151b0bdf1cace092b7892a1e402a27

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feat(imx8ulp): update XRDC for ELE to access DDR with CA35 DID

In order to isolate application memories, ELE FW introduces
a new policy which mimics the requestor attributes (DID, TZ).
So ELE config

feat(imx8ulp): update XRDC for ELE to access DDR with CA35 DID

In order to isolate application memories, ELE FW introduces
a new policy which mimics the requestor attributes (DID, TZ).
So ELE configures SCM to access to external memory with CA35 DID
when CA35 request something from ELE.

Because ELE accesses DDR through NIC_LPAV, the XRDC MRC6 must be
configured for CA35 DID 7 to authorize the access.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I9e91a1b2798e8d15127d1bfa9aa0ffc612fd8981

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feat(imx8ulp): add memory region policy

set the memory region policy for secure heap(0xA9600000 ~ 0xAF600000),
it can only be RWX by secure master. At the same time, restrict G2D
and DCnano(domain 3

feat(imx8ulp): add memory region policy

set the memory region policy for secure heap(0xA9600000 ~ 0xAF600000),
it can only be RWX by secure master. At the same time, restrict G2D
and DCnano(domain 3) to write non-secure memory when they are set as
secure master.

Signed-off-by: Ji Luo <ji.luo@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: If53e130eaeb1ac867ee56e4af04e3be29dec9857

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