docs(cpufeat): clarify description of FEATURE_DETECTION macro

The current documentation of the FEATURE_DETECTION build option seems
to suggest that this macro enables the dynamic runtime checking of

docs(cpufeat): clarify description of FEATURE_DETECTION macro

The current documentation of the FEATURE_DETECTION build option seems
to suggest that this macro enables the dynamic runtime checking of
features, although this is done regardless of this debug feature.
FEATURE_DETECTION just adds the detect_arch_features() function to the
build and calls it early on, plus it enables the CPU errata order
checking.

Simplify the description of the FEATURE_DETECTION macro to make this
clear, and move the dynamic feature detection description into a
separate section, before all the specific ENABLE_FEAT_xxx explanations.

This also renames all mentioning of:
"... to align with the FEATURE_DETECTIION mechanism ..."
with:
"... to align with the ENABLE_FEAT mechanism ..."
in the description of each feature.

Change-Id: I5f4dd2d1e43bd440687b7cee551d02ec853d4e23
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge changes from topics "rcar-tools-fix", "toolchain-cleanup" into integration

* changes:
build: remove the `NM` variable
build: prefer `gcc-ar` over `ar`
build: add `--no-warn-rwx-segments`

Merge changes from topics "rcar-tools-fix", "toolchain-cleanup" into integration

* changes:
build: remove the `NM` variable
build: prefer `gcc-ar` over `ar`
build: add `--no-warn-rwx-segments` when linking with GCC
build: always use the C compiler to assemble
build: always use the C compiler to preprocess
fix(rcar): fix implicit rule invocations in tools

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feat(stm32mp1): only fuse monotonic counter on closed devices

The fused monotonic counter is checked by the ROM bootloader. The ROM
bootloader won't allow booting images build with a lower
STM32_TF_

feat(stm32mp1): only fuse monotonic counter on closed devices

The fused monotonic counter is checked by the ROM bootloader. The ROM
bootloader won't allow booting images build with a lower
STM32_TF_VERSION value.

On non-closed devices a user can easily circumvent this. But it is
annoying for a developer when open development hardware gets the counter
value fused.

Signed-off-by: Robin van der Gracht <robin@protonic.nl>
Change-Id: Ie52561368a3178de9d9a44b9d089664241452651

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Merge "refactor(mte): deprecate CTX_INCLUDE_MTE_REGS" into integration

Merge "feat(qemu-sbsa): handle memory information" into integration

Merge changes from topic "errata" into integration

* changes:
fix(cpus): workaround for Cortex-A78C erratum 2683027
fix(cpus): workaround for Cortex-X3 erratum 2266875
fix(cpus): workaround fo

Merge changes from topic "errata" into integration

* changes:
fix(cpus): workaround for Cortex-A78C erratum 2683027
fix(cpus): workaround for Cortex-X3 erratum 2266875
fix(cpus): workaround for Cortex-X3 erratum 2302506

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refactor(mte): deprecate CTX_INCLUDE_MTE_REGS

Currently CTX_INCLUDE_MTE_REGS is used for dual purpose,
to enable allocation tags register and to context save and restore
them and also to check if mt

refactor(mte): deprecate CTX_INCLUDE_MTE_REGS

Currently CTX_INCLUDE_MTE_REGS is used for dual purpose,
to enable allocation tags register and to context save and restore
them and also to check if mte feature is available.

To make it more meaningful, remove CTX_INCLUDE_MTE_REGS
and introduce FEAT_MTE. This would enable allocation tags register
when FEAT_MTE is enabled and also supported from platform.

Also arch features can be conditionally enabled disabled based on
arch version from `make_helpers/arch_features.mk`

Change-Id: Ibdd2d43874634ad7ddff93c7edad6044ae1631ed
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(imx8mp): uncondtionally enable only the USB power domain

The i.MX8MP exists in multiple SKUs, some of which lack the NPU or VPU.
Yet, we unconditionally enable NPU and VPU power domains in upstr

fix(imx8mp): uncondtionally enable only the USB power domain

The i.MX8MP exists in multiple SKUs, some of which lack the NPU or VPU.
Yet, we unconditionally enable NPU and VPU power domains in upstream
TF-A, causing it to hang on such SoCs, unless patched.

Enabling all power domains is an idiosyncrasy of the i.MX8MP support,
which we don't have on i.MX8MQ, i.MX8MM or i.MX8MN. Therefore let's drop
unconditional powering on of all power domains.

As only exception, we will keep enabling the USB power domains. These
are enabled in the BootROM if booting over SDPS and boot firmware may
expect them to be enabled for non-SDPS recovery too. As USB is
available unconditionally on the current i.MX8MP variants, this is
deemed acceptable and reduces the chance of breaking existing systems.

Fixes: a775ef25c312 ("plat: imx8mp: Add the basic support for i.MX8MP")
Change-Id: Idc6e8f770d240f4d929dffa91f9ccf8c476c6c12
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>

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Merge "fix(intel): update nand driver to match GHRD design" into integration

Merge changes Ib481fade,Id4070b46,I4ac997cd into integration

* changes:
feat(rcar3): update IPL and Secure Monitor Rev.4.0.0
feat(rcar3): add cache operations to boot process
feat(rcar3): chan

Merge changes Ib481fade,Id4070b46,I4ac997cd into integration

* changes:
feat(rcar3): update IPL and Secure Monitor Rev.4.0.0
feat(rcar3): add cache operations to boot process
feat(rcar3): change MMU configurations

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feat(stm32mp2): add BSEC and OTP support

Add compilation and initialization of BSEC peripheral, to access OTP
fuses. Add the definition of OTP fuses.

Signed-off-by: Yann Gautier <yann.gautier@st.co

feat(stm32mp2): add BSEC and OTP support

Add compilation and initialization of BSEC peripheral, to access OTP
fuses. Add the definition of OTP fuses.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: If6403838b1e2c04c59effc8545b381aced5f7cda

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feat(st-bsec): add driver for the new IP version BSEC3

This driver is used for the new version of the BSEC peripheral used
on STM32MP25.

Change-Id: I38ca0db22d06704769c994c6806ccd80b17dde6e
Signed-

feat(st-bsec): add driver for the new IP version BSEC3

This driver is used for the new version of the BSEC peripheral used
on STM32MP25.

Change-Id: I38ca0db22d06704769c994c6806ccd80b17dde6e
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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Merge changes from topic "st-bsec-otp" into integration

* changes:
feat(stm32mp2-fdts): add board ID OTP in STM32MP257F-EV1
feat(stm32mp2-fdts): add OTP nodes in STM32MP251 SoC DT file
fix(stm

Merge changes from topic "st-bsec-otp" into integration

* changes:
feat(stm32mp2-fdts): add board ID OTP in STM32MP257F-EV1
feat(stm32mp2-fdts): add OTP nodes in STM32MP251 SoC DT file
fix(stm32mp2): add missing include
feat(st): do not directly call BSEC functions in common code
feat(st): use stm32_get_otp_value_from_idx() in BL31
refactor(st): update test for closed chip
refactor(st-bsec): improve BSEC driver
refactor(st): use dashes for BSEC node names

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Merge "fix(marvell-tools): include mbedtls/version.h before use" into integration

fix(intel): update nand driver to match GHRD design

Update nand driver to match GHRD design, fix row
address calculation method and other misc updates.

Signed-off-by: Girisha Dengi <girisha.dengi@i

fix(intel): update nand driver to match GHRD design

Update nand driver to match GHRD design, fix row
address calculation method and other misc updates.

Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I1cb3dda43e767ba243fbe89bfa18818db321c5c2

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Merge changes from topic "idling-during-subsystem-restart" into integration

* changes:
fix(xilinx): add console_flush() before shutdown
fix(xilinx): fix sending sgi to linux
feat(xilinx): add

Merge changes from topic "idling-during-subsystem-restart" into integration

* changes:
fix(xilinx): add console_flush() before shutdown
fix(xilinx): fix sending sgi to linux
feat(xilinx): add new state to identify cpu power down
feat(xilinx): request cpu power down from reset
feat(xilinx): power down all cores on receiving cpu pwrdwn req
feat(xilinx): add handler for power down req sgi irq
feat(xilinx): add wrapper to handle cpu power down req
fix(versal-net): use arm common GIC handlers
fix(xilinx): rename macros to align with ARM

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Merge "feat(versal): extend platform address space sizes" into integration

Merge "fix(xilinx): deprecate SiP service count query" into integration

Merge "docs(threat-model): supply chain threat model TF-A" into integration

Merge "feat(rcar3): enable the stack protection" into integration

Merge "docs(security): security advisory for CVE-2023-49100" into integration

feat(qemu-sbsa): handle memory information

As a part of removing DeviceTree from EDK2, we move functions to TF-A:

- counting the number of memory nodes
- checking NUMA node id
- checking the memory

feat(qemu-sbsa): handle memory information

As a part of removing DeviceTree from EDK2, we move functions to TF-A:

- counting the number of memory nodes
- checking NUMA node id
- checking the memory address

Signed-off-by: Xiong Yining <xiongyining1480@phytium.com.cn>
Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: Ib7bce3a65c817a5b3bef6c9e0a459c7ce76c7e35

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feat(rcar3): update IPL and Secure Monitor Rev.4.0.0

Update the version to match release versioning scheme.
No functional change.

Signed-off-by: Hieu Nguyen <hieu.nguyen.dn@renesas.com>
Change-Id:

feat(rcar3): update IPL and Secure Monitor Rev.4.0.0

Update the version to match release versioning scheme.
No functional change.

Signed-off-by: Hieu Nguyen <hieu.nguyen.dn@renesas.com>
Change-Id: Ib481fade925f74dbea1dd2b39c1abfab888379e4

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feat(rcar3): add cache operations to boot process

Add cache operations because BL2 disabled MMU at the end of the boot
process, but did not clean/invalidate for the cache used by MMU.

Signed-off-by

feat(rcar3): add cache operations to boot process

Add cache operations because BL2 disabled MMU at the end of the boot
process, but did not clean/invalidate for the cache used by MMU.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Id4070b46103ca2b50788b3a99f6961a35df24418

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feat(rcar3): change MMU configurations

Always enable MMU and control access protection.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yosh

feat(rcar3): change MMU configurations

Always enable MMU and control access protection.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I4ac997cda2985746b2bf97ab9e4e5ace600f43ca

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