Merge "build: refactor toolchain detection" into integration

Merge "fix(imx8mp): uncondtionally enable only the USB power domain" into integration

feat(smmu): separate out smmuv3_security_init from smmuv3_init

Split the smmuv3_init() to separate smmuv3_security_init() from it in
order to allow skipping the default deny policy on reset for cert

feat(smmu): separate out smmuv3_security_init from smmuv3_init

Split the smmuv3_init() to separate smmuv3_security_init() from it in
order to allow skipping the default deny policy on reset for certain
SMMUv3 implementations.
Additionally, fix a couple of MISRA warnings.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: I2127943e709dd1ded34145bd022c930e351bbb4a

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feat(smmu): fix to perform INV_ALL before enabling GPC

The SMMU_S_INIT register definition in the Arm SMMUv3 specification
says that if SMMUv3 has REALM_IMPL == 1 then it is root firmware’s
responsi

feat(smmu): fix to perform INV_ALL before enabling GPC

The SMMU_S_INIT register definition in the Arm SMMUv3 specification
says that if SMMUv3 has REALM_IMPL == 1 then it is root firmware’s
responsibility to write to INV_ALL before enabling granule protection
checks. So fix this flow during smmuv3 init.

Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Ied9325e1658950c04f06c62485eeab3f28ca1285

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chore(ufs): refactor ufs_get_device_info

Use dedicated function to read device descriptor

Signed-off-by: Rohit Ner <rohitner@google.com>
Change-Id: Ifb90659db7789f33a2b7b01e6eab049395b7fc52

Merge "fix(bl2): make BL2 SRAM footprint flexible" into integration

Merge "docs(sdei): provide security guidelines when using SDEI" into integration

Merge "test(fvp): remove `FVP_Foundation` model support" into integration

Merge "fix(el3-spmc): fix dangling pointer in FFA_CONSOLE_LOG" into integration

fix(psa): fix static check failure

Address the coding style issue that arose from patch [1], which
was inadvertently overlooked during the CI check.

[1]: https://review.trustedfirmware.org/c/TF-A/t

fix(psa): fix static check failure

Address the coding style issue that arose from patch [1], which
was inadvertently overlooked during the CI check.

[1]: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/26263

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I280766fddf0e9e366bb2376c52a6907093b0d958

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Merge changes from topic "mb/tc-model-update" into integration

* changes:
docs: update FVP TC2 model version and build (11.23/17)
fix(tc): increase BL2 maximum size limit
refactor(tc): update

Merge changes from topic "mb/tc-model-update" into integration

* changes:
docs: update FVP TC2 model version and build (11.23/17)
fix(tc): increase BL2 maximum size limit
refactor(tc): update platform tests
feat(rss): add defines for 'type' range and use them in psa_call()
feat(rss): adjust parameter packing to match TF-M changes
refactor(tc): remap console logs

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fix(cm): update gic el2 sysregs save/restore mechanism

This patch does following two changes
- Create a separate routine for saving/restoring GIC el2 system registers
- To access ICC_SRE_EL2 registe

fix(cm): update gic el2 sysregs save/restore mechanism

This patch does following two changes
- Create a separate routine for saving/restoring GIC el2 system registers
- To access ICC_SRE_EL2 register there was a workaround to set
SCR_EL3.NS before accessing it. This was required because SCR_EL3.EEL2
was zero. But with commit f105dd5fa this bit has been set to one early
on in booting process for a system with FEAT_SEL2 present and S-EL2
enabled.
However, we still need the workaround for a system which needs
save/restore of EL2 registers without secure EL2 being enabled e.g.
system with Non-secure and Realm world present.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I8d55c3dc6a17c4749748822d4a738912c1e13298

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docs(sdei): provide security guidelines when using SDEI

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I

docs(sdei): provide security guidelines when using SDEI

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: Ic27bdc88186f6805adee2f452503856e213a4710

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fix(el3-spmc): fix dangling pointer in FFA_CONSOLE_LOG

Fixes a dangling pointer bug in `spmc_ffa_console_log`.
`chars` was assigned to an array which went out of scope at the end of
the `if`/`else`

fix(el3-spmc): fix dangling pointer in FFA_CONSOLE_LOG

Fixes a dangling pointer bug in `spmc_ffa_console_log`.
`chars` was assigned to an array which went out of scope at the end of
the `if`/`else` block.

The solution is to `memcmpy` from the temporary array into `chars`,
which is now an array.

Signed-off-by: Karl Meakin <karl.meakin@arm.com>
Change-Id: I67d19ea25d09b72f38fcc67dab4acf449aa8f1b1

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docs(threat_model): mark power analysis threats out-of-scope

Exclude the threat of power analysis side-channel attacks
from consideration in the TF-A generic threat model.

Signed-off-by: Manish V B

docs(threat_model): mark power analysis threats out-of-scope

Exclude the threat of power analysis side-channel attacks
from consideration in the TF-A generic threat model.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I5b245f33609fe8948e473ce4484898db5ff8db4d

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Merge changes from topic "DPE" into integration

* changes:
feat(tc): add RSS SDS region right after SCMI payload
refactor(n1sdp): update SDS driver calls
refactor(morello): update SDS driver c

Merge changes from topic "DPE" into integration

* changes:
feat(tc): add RSS SDS region right after SCMI payload
refactor(n1sdp): update SDS driver calls
refactor(morello): update SDS driver calls
refactor(juno): update SDS driver calls
refactor(sgi): update SDS driver calls
refactor(css): support multiple SDS regions

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fix(bl2): make BL2 SRAM footprint flexible

On FVP's the default SRAM size is severly restrictive. However, more
recent models support larger SRAM configurations (> 256 Kb). We
introduced the flag FV

fix(bl2): make BL2 SRAM footprint flexible

On FVP's the default SRAM size is severly restrictive. However, more
recent models support larger SRAM configurations (> 256 Kb). We
introduced the flag FVP_TRUSTED_SRAM_SIZE to allow for TF to handle
different configurations.

BL31 automatically benefits from this optimisation since it starts from
the bottom of shared memory, and runs up to the end of SRAM. Increase
the size of all BL2 builds in proportion to FVP_TRUSTED_SRAM_SIZE so
that BL2 covers around a third of SRAM.

Change-Id: Idf37e8cb86507ea44b97ac8b3b90fffefe13f57a
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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docs: update FVP TC2 model version and build (11.23/17)

Update the FVP TC2 model version and build (11.23/17) to match
the version used for testing in TF-A OpenCI.

Signed-off-by: Manish V Badarkhe

docs: update FVP TC2 model version and build (11.23/17)

Update the FVP TC2 model version and build (11.23/17) to match
the version used for testing in TF-A OpenCI.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ic7411ee4863428b7dfbe43cf39abfc2269f3c3ae

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fix(tc): increase BL2 maximum size limit

Increase the size of BL2 to build TC2 with GPT support enabled
and a config modification of mbedTLS.

Change-Id: I6d2f466144f2bbffd3387bc40bc86ab733febce1
Si

fix(tc): increase BL2 maximum size limit

Increase the size of BL2 to build TC2 with GPT support enabled
and a config modification of mbedTLS.

Change-Id: I6d2f466144f2bbffd3387bc40bc86ab733febce1
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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refactor(tc): update platform tests

Update the TC's platform test Makefile and related common definitions
to correspond to newer TF-M code (commit hash: 4ab7a20).

Change-Id: I6ef3effe194a780a0533f9

refactor(tc): update platform tests

Update the TC's platform test Makefile and related common definitions
to correspond to newer TF-M code (commit hash: 4ab7a20).

Change-Id: I6ef3effe194a780a0533f9c0c2eab9d0f4efc1fc
Signed-off-by: David Vincze <david.vincze@arm.com>

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feat(rss): add defines for 'type' range and use them in psa_call()

Update the 'type' parameter checking according to changes
on RSS's (TF-M) side: 40b09ba1 [1]

[1]: https://git.trustedfirmware.org/

feat(rss): add defines for 'type' range and use them in psa_call()

Update the 'type' parameter checking according to changes
on RSS's (TF-M) side: 40b09ba1 [1]

[1]: https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/commit/?id=40b09ba1e4a7a4f726f98700eab7e4e4d8e95dcf

Change-Id: I8487e8ab24aa2dd080b5bb8f2f5c7e8fc15cf211
Signed-off-by: David Vincze <david.vincze@arm.com>

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feat(rss): adjust parameter packing to match TF-M changes

Adjust the parameter packing scheme in RSS communication
to align with changes made in TF-M: 3be6c395 [1]

[1]: https://git.trustedfirmware.

feat(rss): adjust parameter packing to match TF-M changes

Adjust the parameter packing scheme in RSS communication
to align with changes made in TF-M: 3be6c395 [1]

[1]: https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/commit/?id=3be6c3954b94f000cdcf7575bd4c18f57b3492f8

Change-Id: Ief38f96ab991d1125b37adfced5ffafc39e754a0
Signed-off-by: David Vincze <david.vincze@arm.com>

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refactor(tc): remap console logs

Remap TF-A console logs from SoC UART2 (S1 terminal) to CSS
secure (UART1_AP terminal) and Linux logs from SoC UART2
(S1 terminal) to CSS non-secure (UART_AP termina

refactor(tc): remap console logs

Remap TF-A console logs from SoC UART2 (S1 terminal) to CSS
secure (UART1_AP terminal) and Linux logs from SoC UART2
(S1 terminal) to CSS non-secure (UART_AP terminal) to align
with the latest FVP TC2 model (version 11.23/17).

Change-Id: I7206e64b65346bfdcc48d6acd3792b436041e45f
Signed-off-by: Annam Sai Manisha <annam.saimanisha@arm.com>

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feat(tc): add RSS SDS region right after SCMI payload

Add a second SDS region on the TC platform for communication with RSS.
RSS needs to share data with AP during early boot over shared memory
to s

feat(tc): add RSS SDS region right after SCMI payload

Add a second SDS region on the TC platform for communication with RSS.
RSS needs to share data with AP during early boot over shared memory
to support DPE. Reserve a memory region right after the SCMI secure
payload areas from unused memory.

Change-Id: I3a3a6ea5ce76531595c88754418602133a283c42
Signed-off-by: David Vincze <david.vincze@arm.com>

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refactor(n1sdp): update SDS driver calls

Update SDS driver calls to align with recent
changes [1] of the SDS driver.

- The driver now requires us to explicitly pass
the SDS region id to act on.
-

refactor(n1sdp): update SDS driver calls

Update SDS driver calls to align with recent
changes [1] of the SDS driver.

- The driver now requires us to explicitly pass
the SDS region id to act on.
- Implement plat_sds_get_regions() platform function
which is used by the driver to get SDS region
information per platform.

[1]: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/24609/

Change-Id: I3447855fbe7427376d5f7aa0ba7356fe2f14d567
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Signed-off-by: David Vincze <david.vincze@arm.com>

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