refactor(neoverse-rd): header files for first generation platforms

Presently, platforms such as SGI-575, RD-N1-Edge single and dual chip,
RD_V1 single and multi-chip utilize nrd_soc_platform_def.h a

refactor(neoverse-rd): header files for first generation platforms

Presently, platforms such as SGI-575, RD-N1-Edge single and dual chip,
RD_V1 single and multi-chip utilize nrd_soc_platform_def.h and
nrd_soc_css_def.h for all css and soc-related defines. So move these
two header files into a new directory named 'nrd1'. This new directory
will serve as the container of header files that are specific to
SGI-575, RD-N1 and RD-V1 platform and its variants.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I9d70659c6f5000ad6c1cfc0738f9e81f03238f5f

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refactor(neoverse-rd): refactor scope for Neoverse RD platforms

As sgi has migrated to neoverse_rd, the scope variables would need
update. Therefore, remove the deprecated 'sgi' scope variable and
i

refactor(neoverse-rd): refactor scope for Neoverse RD platforms

As sgi has migrated to neoverse_rd, the scope variables would need
update. Therefore, remove the deprecated 'sgi' scope variable and
introduce the new scope variable 'neoverse-rd' to be used for any common
platform changes associated with Neoverse Reference Design platforms.

Change-Id: I5052e4573bdc7df3e6f4257146d716edd2585452
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>

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Merge changes from topic "st_maintainers" into integration

* changes:
docs(maintainers): add missing ST files
docs(maintainers): add Maxime as co-maintainer for ST platforms
docs(maintainers):

Merge changes from topic "st_maintainers" into integration

* changes:
docs(maintainers): add missing ST files
docs(maintainers): add Maxime as co-maintainer for ST platforms
docs(maintainers): update ST platform ports title
docs(maintainers): sort github aliases

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feat(stm32mp2): use early traces

Replace ERROR message with EARLY_ERROR for OTP driver probe, as this
will be called before default console is enabled.

Signed-off-by: Yann Gautier <yann.gautier@st.

feat(stm32mp2): use early traces

Replace ERROR message with EARLY_ERROR for OTP driver probe, as this
will be called before default console is enabled.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I756a04727c494d5f681a45d47d01189dff07dbe7

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feat(st-bsec): use early traces

Replace trace macros with their corresponding EARLY_* macros.
Add some early traces in bsec2 driver.

Change-Id: I65e2feee6e7ba2524fb0a334557aa6e883672765
Signed-off-

feat(st-bsec): use early traces

Replace trace macros with their corresponding EARLY_* macros.
Add some early traces in bsec2 driver.

Change-Id: I65e2feee6e7ba2524fb0a334557aa6e883672765
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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refactor(st): replace STM32MP_EARLY_CONSOLE with EARLY_CONSOLE

Now that EARLY_CONSOLE is generic, use it instead of the ST flag.
Remove stm32mp_setup_early_console() calls as it is done in common TF

refactor(st): replace STM32MP_EARLY_CONSOLE with EARLY_CONSOLE

Now that EARLY_CONSOLE is generic, use it instead of the ST flag.
Remove stm32mp_setup_early_console() calls as it is done in common TF-A
code.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Icac29b62a6267303cb5c679d15847c013ead1d23

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feat(console): introduce EARLY_CONSOLE

This is a generic porting of what was done on ST platforms with flag
STM32MP_EARLY_CONSOLE. It creates the flag and the prototype for
plat_setup_early_console(

feat(console): introduce EARLY_CONSOLE

This is a generic porting of what was done on ST platforms with flag
STM32MP_EARLY_CONSOLE. It creates the flag and the prototype for
plat_setup_early_console(). This function depends on platform
implementation. This function call is added at the beginning of each BL
image early setup function.
The patch also introduce an extra log macro: EARLY_ERROR. This can
replace ERROR macro in code that will only be executed before the
default console is enabled, and will do nothing when the EARLY_CONSOLE
is not enabled. This can then save some space in memory.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I77bf0a0c4289b4c7df94e4bfb783a938e05bf023

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feat(bl32): create an sp_min_setup function

This new C function will call sp_min_early_platform_setup2() and
sp_min_plat_arch_setup(). At this step the C environment is already
enabled, and it allow

feat(bl32): create an sp_min_setup function

This new C function will call sp_min_early_platform_setup2() and
sp_min_plat_arch_setup(). At this step the C environment is already
enabled, and it allows adding function like the one for early console
for which r9-r12 registers could be clobbered.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I4cbf2f6acea769d595ff40b2e2b4ca5d29672878

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Merge "docs(fconf): add TB_FW config bindings" into integration

Merge "fix(cert-create): add guardrails around brainpool usage" into integration

Merge "fix(cert-create): use a salt length equal to digest length for RSA-PSS" into integration

refactor(docs): restructure min requirements section

The ordering of the setup guide is quite confusing, primarly because the
min requirements section is overly verbose. Reconcile this information
i

refactor(docs): restructure min requirements section

The ordering of the setup guide is quite confusing, primarly because the
min requirements section is overly verbose. Reconcile this information
into a single table, and present the most important information at the
start of the document i.e. how to get the source, and the tools to
compile.

Change-Id: I1c4d708259e152b101c7282dad19e467d6c36519
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge "fix(cpus): workaround for Cortex-X4 erratum 2763018" into integration

fix(cpus): workaround for Cortex-X4 erratum 2763018

Cortex-X4 erratum 2763018 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2.

The workaround is to set bit[47] of CP

fix(cpus): workaround for Cortex-X4 erratum 2763018

Cortex-X4 erratum 2763018 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2.

The workaround is to set bit[47] of CPUACTLR3_EL1 register.
Setting this chicken bit might have a small impact on power
and negligible impact on performance.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2432808/latest

Change-Id: Ia188e08c2eb2952923ec72e2a56efdeea836fe1e
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(optee): set interrupt handler before kernel boot

When loading OPTEE via an SMC after we start Linux, we end up changing
the interrupt settings which is a violation of the Linux kernel's
policies

fix(optee): set interrupt handler before kernel boot

When loading OPTEE via an SMC after we start Linux, we end up changing
the interrupt settings which is a violation of the Linux kernel's
policies. This change sets the interrupt handler before we proceed to
starting the kernel and ignores any incoming interrupts that occur
before OPTEE is loaded.

Signed-off-by: Jeffrey Kardatzke<jkardatzke@google.com>
Change-Id: I7da5334498e14f4a703e8cc3eeff386e3ecc0882

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Merge "refactor(fvp_r): remove duplicated macro definitions" into integration

Merge "fix(cpus): workaround for Cortex-X4 erratum 2740089" into integration

Merge "fix(cpus): workaround for Cortex-A715 erratum 2728106" into integration

Merge "feat(qemu): update to manifest v0.3" into integration

feat(qemu): update to manifest v0.3

Update the RMM manifest to v0.3: pass the console information to RMM.

Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Change-Id: I55093cd0c12f9c6

feat(qemu): update to manifest v0.3

Update the RMM manifest to v0.3: pass the console information to RMM.

Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Change-Id: I55093cd0c12f9c6a7569d7e524f7d301acbb2a45

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Merge "feat(qemu): allow ARM_ARCH_MAJOR/MINOR override" into integration

Merge "feat(qemu): enable FEAT_ECV when present" into integration

fix(tc): remove timer interrupt from G1S

TC3 and TC4 SCP makes use of the system timer interrupt as its own
timer. Previously, this timer was marked as a G1S interrupt which
routes the interrupt to

fix(tc): remove timer interrupt from G1S

TC3 and TC4 SCP makes use of the system timer interrupt as its own
timer. Previously, this timer was marked as a G1S interrupt which
routes the interrupt to the secure world and also enables it. This
causes spurious interrupts once the SCP has unmasked the interrupt in
the timer control itself.

Note that we move the inclusion of the timer interrupt from
CSS_G1S_INT_PROPS to CSS_G1S_IRQ_PROPS as the former is only used by TC.
This will also result in removing the timer interrupt from TC2. This is
not an issue as it does not make use of this interrupt in either the SCP
or AP.

Change-Id: I5cc88e2adffbc93fc3c9d9d41b5ba7235dbc39d9
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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Merge "refactor(qemu): do not hardcode counter frequency" into integration

Merge "fix(cm): add more feature registers to EL1 context mgmt" into integration