Merge "fix(mte): use ATA bit with FEAT_MTE2" into integration

Merge "refactor(cm): minor update on conditions used in prepare_el3_exit" into integration

Merge "chore: update status of Cortex-X3 erratum 2615812" into integration

Merge "fix(nuvoton): gfx frame buffer memory corruption during secondary boot" into integration

Merge "fix(cpus): workaround for Cortex-A720 erratum 2940794" into integration

Merge "fix(mhu): use MHUv2 if PLAT_MHU_VERSION undefined" into integration

fix(mhu): use MHUv2 if PLAT_MHU_VERSION undefined

If RSS Comms is used but PLAT_MHU_VERSION was undefined then it should
default to MHUv2 to avoid breaking existing configurations which did not
need

fix(mhu): use MHUv2 if PLAT_MHU_VERSION undefined

If RSS Comms is used but PLAT_MHU_VERSION was undefined then it should
default to MHUv2 to avoid breaking existing configurations which did not
need to specify PLAT_MHU_VERSION as on MHUv2 was available.

Change-Id: I8353b49b9f61414a664c2802f90ba3b2bc526887
Signed-off-by: Joel Goddard <joel.goddard@arm.com>

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Merge changes from topic "st_docs_update" into integration

* changes:
docs(st): set OP-TEE as default BL32
docs(st): one device flag for ST platforms

Merge changes from topic "st_mckprot_bl32" into integration

* changes:
refactor(stm32mp1): move the MCU security to BL32
feat(st-clock): add function to control MCU subsystem

chore: update status of Cortex-X3 erratum 2615812

SDEN documentation:
https://developer.arm.com/documentation/2055130/latest

Change-Id: Ied7150bab505a743401cf4afa9a0a5f81d5fdff1
Signed-off-by: Sona

chore: update status of Cortex-X3 erratum 2615812

SDEN documentation:
https://developer.arm.com/documentation/2055130/latest

Change-Id: Ied7150bab505a743401cf4afa9a0a5f81d5fdff1
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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Merge changes from topic "tfa_mhuv3" into integration

* changes:
feat(mhu): use compile flag to choose mhu version
feat(mhu): add MHUv3 wrapper APIs for RSS comm driver
feat(mhu): add MHUv3 do

Merge changes from topic "tfa_mhuv3" into integration

* changes:
feat(mhu): use compile flag to choose mhu version
feat(mhu): add MHUv3 wrapper APIs for RSS comm driver
feat(mhu): add MHUv3 doorbell driver

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Merge "refactor: fix common misspelling of init*" into integration

refactor: fix common misspelling of init*

Change-Id: I3fc95e8e53ef487fd5a559cda739aaea33d765a9
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

refactor(cm): minor update on conditions used in prepare_el3_exit

This patch covers the following:

* Conditions set for verifying the EL2 presence and its usage
for various scenarios while exitin

refactor(cm): minor update on conditions used in prepare_el3_exit

This patch covers the following:

* Conditions set for verifying the EL2 presence and its usage
for various scenarios while exiting to Non secure world
"cm_prepare_el3_exit" has been improved.

* It thereby also fixes the issue(misra_c_2012_rule_15_7_violation)
for not terminating "if..else if" construct with an else statement
and keeps code in accordance with MISRA standards.

Change-Id: Ie5284447f5ac91412552629b76dbf2e636a09fd9
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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fix(cpus): workaround for Cortex-A720 erratum 2940794

Cortex-A720 erratum 2940794 is a Cat B erratum that is present
in revision r0p0, r0p1 and is fixed in r0p2.

The workaround is to set bit[37] of

fix(cpus): workaround for Cortex-A720 erratum 2940794

Cortex-A720 erratum 2940794 is a Cat B erratum that is present
in revision r0p0, r0p1 and is fixed in r0p2.

The workaround is to set bit[37] of the CPUACTLR2_EL1 to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2439421/latest

Change-Id: I1488802e0ec7c16349c9633bb45de4d0e1faa9ad
Signed-off-by: Bipin Ravi <biprav01@u203721.austin.arm.com>

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feat(rcar3): change CAM setting to improve bus latency of R-Car Gen3

In the high system load situation, bus latency increase was observed
and it made impact to other feature (e.g. audio dropouts). T

feat(rcar3): change CAM setting to improve bus latency of R-Car Gen3

In the high system load situation, bus latency increase was observed
and it made impact to other feature (e.g. audio dropouts). This is
because some modules push as much as possible traffic into the DBSC4
CAM for execution, and make increasing bus latency. Re-defining swap
priorities reduce this situation. This advice has been confirmed by
hardware developer.

Signed-off-by: Dien Pham <dien.pham.ry@renesas.com>
Change-Id: Ifebafa883d5a997de6894198327a6025b64e4ee5

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refactor(stm32mp1): move the MCU security to BL32

Change the MCKPROT control management. Now, the MCU subsystem
is done in the BL32 using the dedicated clock function.
If using OP-TEE, you will need

refactor(stm32mp1): move the MCU security to BL32

Change the MCKPROT control management. Now, the MCU subsystem
is done in the BL32 using the dedicated clock function.
If using OP-TEE, you will need the corresponding commit [1].
This should be integrated in OP-TEE tag 4.2.0.

[1] e07f9212d5 plat-stm32mp1: shared_resource: disable MCKPROT if
not needed

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I59f90ace750aa93f674389f881e2fe14ad334a72

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feat(st-clock): add function to control MCU subsystem

Add a new function to control the MCU subsystem
security state.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I070eec06fc93a

feat(st-clock): add function to control MCU subsystem

Add a new function to control the MCU subsystem
security state.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I070eec06fc93a1214227f25a6a4f1c40c66c86b0

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Merge "docs(threat_model): cover the 'timing' side channel threat" into integration

docs(threat_model): cover the 'timing' side channel threat

Incorporate a timing side-channel attack into the TF-A generic
threat model. There is no software mitigation measures in TF-A
against this

docs(threat_model): cover the 'timing' side channel threat

Incorporate a timing side-channel attack into the TF-A generic
threat model. There is no software mitigation measures in TF-A
against this specific type of attack.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I10e53f8ed85a6da32de4fa6a210805f950018102

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docs(st): set OP-TEE as default BL32

Recommend OP-TEE as the default BL32 for STMicroelectronics platforms.
SP_MIN is no more supported in STMicroelectronics software [1].
It will then no more recei

docs(st): set OP-TEE as default BL32

Recommend OP-TEE as the default BL32 for STMicroelectronics platforms.
SP_MIN is no more supported in STMicroelectronics software [1].
It will then no more receive new features, but should still remain
as it is in the TF-A code.

[1]: https://wiki.st.com/stm32mpu/wiki/STM32_MPU_OpenSTLinux_release_note_-_v5.0.0#TF-A

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ic49338dbba3fdcebcb1e477e6a1dbde32783482b

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docs(st): one device flag for ST platforms

Due to embedded SRAM used to load BL2 and BL31 or BL32 has a limited
size, only one storage device or serial device flag should be selected
in TF-A build c

docs(st): one device flag for ST platforms

Due to embedded SRAM used to load BL2 and BL31 or BL32 has a limited
size, only one storage device or serial device flag should be selected
in TF-A build command line for ST platforms.
This is in line with STMicroelectionics recommendation [1] about those
compilation flags.

[1]: https://wiki.st.com/stm32mpu/wiki/How_to_configure_TF-A_BL2#Build_command_details

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I6f6ab17d45d00289989a606d15c143e5710c64ce

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Merge "refactor(guid-partition): list.entry_count to unsigned int" into integration

fix(nuvoton): gfx frame buffer memory corruption during secondary boot

gfx frame buffer memory corruption because of moving TF-A to DDR

Change-Id: I6f1e0c8d048273b8047497adec631160aaf393d6
Signed-o

fix(nuvoton): gfx frame buffer memory corruption during secondary boot

gfx frame buffer memory corruption because of moving TF-A to DDR

Change-Id: I6f1e0c8d048273b8047497adec631160aaf393d6
Signed-off-by: Margarita Glushkin <rutigl@gmail.com>

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fix(mte): use ATA bit with FEAT_MTE2

Currently SCR_EL3.ATA bit(26) is used freely or either with FEAT_MTE,
But ATA bit is available only with FEAT_MTE2. So use FEAT_MTE2
conditional check for use of

fix(mte): use ATA bit with FEAT_MTE2

Currently SCR_EL3.ATA bit(26) is used freely or either with FEAT_MTE,
But ATA bit is available only with FEAT_MTE2. So use FEAT_MTE2
conditional check for use of SCR_EL3.ATA.

Ref:
https://developer.arm.com/documentation/ddi0601/2023-12/AArch64-Registers/SCR-EL3--Secure-Configuration-Register?lang=en#fieldset_0-26_26-1

Change-Id: I0a5766a138b0be760c5584014f1ab817e4207a93
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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