Merge "fix(spmd): register group0 handler only if supported" into integration

Merge "fix(build): don't rely on that gcc-ar is in the same directory as gcc" into integration

build: use GCC to link by default

When configuring GNU GCC as the C compiler, we usually use the GNU BFD
linker directly to link by default. However, this complicates things
because we also need to

build: use GCC to link by default

When configuring GNU GCC as the C compiler, we usually use the GNU BFD
linker directly to link by default. However, this complicates things
because we also need to support LTO, which can only be done when linking
is done via the C compiler, and we cannot change the linker later on if
some other part of the build system wants to enable LTO.

This change migrates the default choice of linker to GCC if the C
compiler is GCC, in order to enable this use-case. This should have no
impact on anything outside of the build system, as by default GCC merely
acts as a wrapper around BFD.

Change-Id: I40771be2b0571def67bbfde9e877e7629ec8cdaa
Signed-off-by: Chris Kay <chris.kay@arm.com>

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fix(cm): save guarded control stack registers

This patch fixes a typo which led to incorrect context save
operations for two FEAT_GCS registers.

Change-Id: I3d3202a6721714bbc8f84c2d775d1b28afffa5df

fix(cm): save guarded control stack registers

This patch fixes a typo which led to incorrect context save
operations for two FEAT_GCS registers.

Change-Id: I3d3202a6721714bbc8f84c2d775d1b28afffa5df
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge "fix(nuvoton): prevent changing clock frequency" into integration

Merge "feat(imx8mq): detect console base address during runtime" into integration

Merge "feat(xilinx): send SGI to mailbox driver" into integration

feat(imx8mq): detect console base address during runtime

On the i.MX8M SoCs, TF-A doesn't itself initialize the UART, but depends
on BL2 to set it up beforehand. To allow using the same TF-A binary

feat(imx8mq): detect console base address during runtime

On the i.MX8M SoCs, TF-A doesn't itself initialize the UART, but depends
on BL2 to set it up beforehand. To allow using the same TF-A binary on
boards with different UART assignment, TF-A On i.MX8M M/N/P supports
dynamically determining the UART in use. The code is also applicable to
the i.MX8MQ, so enable it there too.

Change-Id: I9ba70f7068e762da979bd103390fa006c3a5d480
Signed-off-by: Leonard Göhrs <l.goehrs@pengutronix.de>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>

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Merge "feat(rcar3): change CAM setting to improve bus latency of R-Car Gen3" into integration

fix(spmd): register group0 handler only if supported

For platforms that do not support EL3 interrupts, such as ones with
GICV2 controller, do not register handler for Group0 interrupt.

Change-Id: I

fix(spmd): register group0 handler only if supported

For platforms that do not support EL3 interrupts, such as ones with
GICV2 controller, do not register handler for Group0 interrupt.

Change-Id: I34536c0db9806c7b4c12dd398c0e5c12119c7457
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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feat(xilinx): send SGI to mailbox driver

Generate SGI to mailbox driver if IPI FIQ occurs due to agents
other than PMC.

Change-Id: Ieefb9f0db4009fe0179b18d30da153ce3f9e134c
Signed-off-by: Tanmay Sh

feat(xilinx): send SGI to mailbox driver

Generate SGI to mailbox driver if IPI FIQ occurs due to agents
other than PMC.

Change-Id: Ieefb9f0db4009fe0179b18d30da153ce3f9e134c
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>

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Merge changes from topic "mte_fixes" into integration

* changes:
build(changelog): move mte to mte2
refactor(mte): remove mte, mte_perm

build(changelog): move mte to mte2

With commit:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/27122?tab=comments

FEAT_MTE is removed and we have only FEAT_MTE2, so update change lo

build(changelog): move mte to mte2

With commit:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/27122?tab=comments

FEAT_MTE is removed and we have only FEAT_MTE2, so update change log
to reflect the same.

Change-Id: I9f3bd7053f9c1fa355168968f412374e1c4937d4
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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refactor(mte): remove mte, mte_perm

Currently both FEAT_MTE and FEAT_MTE_PERM aren't used for enabling
of any feature bits in EL3. So remove both FEAT handling.

All mte regs that are currently cont

refactor(mte): remove mte, mte_perm

Currently both FEAT_MTE and FEAT_MTE_PERM aren't used for enabling
of any feature bits in EL3. So remove both FEAT handling.

All mte regs that are currently context saved/restored are needed
only when FEAT_MTE2 is enabled, so move to usage of FEAT_MTE2 and
remove FEAT_MTE usage.

BREAKING CHANGE: Any platform or downstream code trying to use
SCR_EL3.ATA bit(26) will see failures as this is now moved to be
used only with FEAT_MTE2 with
commit@ef0d0e5478a3f19cbe70a378b9b184036db38fe2

Change-Id: Id01e154156571f7792135639e17dc5c8d0e17cf8
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge "chore: rename Poseidon to Neoverse V3" into integration

chore: rename Poseidon to Neoverse V3

Rename Neoverse Poseidon to Neoverse V3, make changes
to related build flags, macros, file names etc.

Change-Id: I9e40ba8f80b7390703d543787e6cd2ab6301e891
Sign

chore: rename Poseidon to Neoverse V3

Rename Neoverse Poseidon to Neoverse V3, make changes
to related build flags, macros, file names etc.

Change-Id: I9e40ba8f80b7390703d543787e6cd2ab6301e891
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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Merge changes from topic "feature/imx8m-csu" into integration

* changes:
style(imx8m): add parenthesis to CSU_HP_REG
feat(imx8mp): restrict peripheral access to secure world
feat(imx8mp): set

Merge changes from topic "feature/imx8m-csu" into integration

* changes:
style(imx8m): add parenthesis to CSU_HP_REG
feat(imx8mp): restrict peripheral access to secure world
feat(imx8mp): set and lock almost all peripherals as non-secure
feat(imx8mm): restrict peripheral access to secure world
feat(imx8mm): set and lock almost all peripherals as non-secure
feat(imx8m): add defines for csu_sa access security
feat(imx8m): add imx csu_sa enum type defines for imx8m
fix(imx8m): fix CSU_SA_REG to work with all sa registers

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Merge "feat(imx8ulp): give HIFI4 DSP access to more resources" into integration

fix(nuvoton): prevent changing clock frequency

prevent changing clock frequency already set in BootBlock based on PLL value

Change-Id: I8b4b53448cc8e703fd88ad6166f85a4fe3ba9e46
Signed-off-by: Marga

fix(nuvoton): prevent changing clock frequency

prevent changing clock frequency already set in BootBlock based on PLL value

Change-Id: I8b4b53448cc8e703fd88ad6166f85a4fe3ba9e46
Signed-off-by: Margarita Glushkin <rutigl@gmail.com>

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feat(imx8ulp): give HIFI4 DSP access to more resources

This patch gives i.MX8ULP's HIFI4 DSP R/W access to the
following additional resources (peripherals):
1) LPUART7
2) IOMUXC1
3) PCC4
4) CGC1

feat(imx8ulp): give HIFI4 DSP access to more resources

This patch gives i.MX8ULP's HIFI4 DSP R/W access to the
following additional resources (peripherals):
1) LPUART7
2) IOMUXC1
3) PCC4
4) CGC1

Doing this allows the firmware running on the DSP to
set up serial communication, which also requires doing
pinctrl and clock management-related operations.

Access to the aforementioned resources is given by
configuring the XRDC module.

Change-Id: Ie3ca9f22bb625b2463870158875f503c3c1d6452
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>

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Merge "fix(cpus): workaround for Cortex-A715 erratum 2413290" into integration

Merge "fix(cpus): workaround for Cortex-A720 erratum 2926083" into integration

fix(cpus): workaround for Cortex-A715 erratum 2413290

Erratum 2413290 is a Cat B erratum that is present only
in revision r0p1 and is fixed in r1p1.

The initial implementation did not consider that

fix(cpus): workaround for Cortex-A715 erratum 2413290

Erratum 2413290 is a Cat B erratum that is present only
in revision r0p1 and is fixed in r1p1.

The initial implementation did not consider that this
fix is to be applied only when SPE (Statistical Profiling
Extension) is implemented and enabled. This patch applies
the fix by adding a check for ENABLE_SPE_FOR_NS.

Change-Id: I87b2175b89d6fb168c77e6ab233c90ca056791a1
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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Merge changes Id72a0370,I2bafba38,I2bd48441,I164c579c,Iddf8aea0, ... into integration

* changes:
feat(rpi): add Raspberry Pi 5 support
fix(rpi): consider MT when calculating core index from MPID

Merge changes Id72a0370,I2bafba38,I2bd48441,I164c579c,Iddf8aea0, ... into integration

* changes:
feat(rpi): add Raspberry Pi 5 support
fix(rpi): consider MT when calculating core index from MPIDR
refactor(rpi): move register definitions out of rpi_hw.h
refactor(rpi): add platform macro for the crash UART base address
refactor(rpi): split out console registration logic
refactor(rpi): move more platform-specific code into common

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fix(cpus): workaround for Cortex-A720 erratum 2926083

Cortex-A720 erratum 2926083 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2. The errata is only
present when SPE

fix(cpus): workaround for Cortex-A720 erratum 2926083

Cortex-A720 erratum 2926083 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2. The errata is only
present when SPE (Statistical Profiling Extension) is implemented
and enabled.

The workaround is to set bits[58:57] of the CPUACTLR_EL1 to 'b11
when SPE is "implemented and enabled".

SDEN documentation:
https://developer.arm.com/documentation/SDEN2439421/latest

Change-Id: I30182c3893416af65b55fca9a913cb4512430434
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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