Merge "docs(build): update GCC to 13.2.Rel1 version" into integration

feat(qemu): enable FEAT_ECV when present

QEMU supports FEAT_ECV since commit 2808d3b38a52 ("target/arm: Implement
FEAT_ECV CNTPOFF_EL2 handling"), in the v9.0.0 release. Enable
auto-detecting the fe

feat(qemu): enable FEAT_ECV when present

QEMU supports FEAT_ECV since commit 2808d3b38a52 ("target/arm: Implement
FEAT_ECV CNTPOFF_EL2 handling"), in the v9.0.0 release. Enable
auto-detecting the feature on the QEMU platforms, in order to set
SCR.ECVEN. Without this, EL2 gets undefined instruction exceptions when
trying to access the new CNTPOFF register.

Change-Id: I555a5f9a9a84fd23e64ca85219ed1599204c6bb2
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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Merge "fix(ff-a): add NS memory node to fvp_spmc_optee_sp manifest" into integration

refactor(fvp): reduce max size of HW_CONFIG to 16KB

HW_CONFIG is the hardware description consumed primarly by the Linux
kernel, and for the FVP platform, TF-A runtime firmware (BL31). Due to
both n

refactor(fvp): reduce max size of HW_CONFIG to 16KB

HW_CONFIG is the hardware description consumed primarly by the Linux
kernel, and for the FVP platform, TF-A runtime firmware (BL31). Due to
both needing it, two copies of this file are made in Trusted DRAM and
SRAM. The copy in Trusted DRAM is a workaround stemming from memory
constraints in SRAM. We temporarily map the range of memory in Trusted
DRAM into BL31 to allow it to consume the configuration. In principle,
however, BL31 execution should be limited to SRAM, hence reduce the
maximum size of the HW_CONFIG to 16KB in order to accommodate it in
SRAM. This is possible since in practice, the HW_CONFIG on FVP is only
about 11KB.

Change-Id: Idb5dc0637b402562b7177a2b4e2464c4f3f67da7
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(locks): add bitlock

This patch adds 'bitlock_t' type and bit_lock() and
bit_unlock() to support locking/release functionality
based on individual bit position. These functions use
atomic bit se

feat(locks): add bitlock

This patch adds 'bitlock_t' type and bit_lock() and
bit_unlock() to support locking/release functionality
based on individual bit position. These functions use
atomic bit set and clear instructions which require
FEAT_LSE mandatory from Armv8.1.

Change-Id: I3eb0f29bbccefe6c0f69061aa701187a6364df0c
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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fix(intel): f2sdram bridge quick write thru failed

This patch is to fix the f2sdram bridge quick write thru failing by
removing the clear bit for sidebandmgr flagout register.

Change-Id: Ib03498fbb

fix(intel): f2sdram bridge quick write thru failed

This patch is to fix the f2sdram bridge quick write thru failing by
removing the clear bit for sidebandmgr flagout register.

Change-Id: Ib03498fbb2d91e9fd85f6315091ff72cbe3f394d
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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fix(gicv2): fix SGIR_NSATT bitshift

See https://documentation-service.arm.com/static/5f8ff196f86e16515cdbf969?token=

Fixes: dcb31ff79096fc88b45df8068e5de83b93f833ed

Signed-off-by: Jacob Kroon <jac

fix(gicv2): fix SGIR_NSATT bitshift

See https://documentation-service.arm.com/static/5f8ff196f86e16515cdbf969?token=

Fixes: dcb31ff79096fc88b45df8068e5de83b93f833ed

Signed-off-by: Jacob Kroon <jacob.kroon@gmail.com>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I79ef17c4538cc3e2d65fedd4dfc2eacf55167bf6

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fix(cert-create): use a salt length equal to digest length for RSA-PSS

Currently when RSA-PSS signing is invoked, a salt length of 32 bytes
is assumed. This works well when SHA-256 is the digest alg

fix(cert-create): use a salt length equal to digest length for RSA-PSS

Currently when RSA-PSS signing is invoked, a salt length of 32 bytes
is assumed. This works well when SHA-256 is the digest algorithm, but
the standard industry practice is that the salt length should follow
the digest length (e.g. 48/64 bytes for SHA-384/SHA-512).

Various cloud services' key management services (KMS) offering have
such restrictions in place, so if someone wants to integrate cert_create
against these services for signing key/content certs, they will have
problem with integration.

Furthermore, JWS (RFC7518) defined these specific combinations as valid
specs and other combinations are not supported:

- PS256: RSASSA-PSS using SHA-256 and MGF1 with SHA-256
- PS384: RSASSA-PSS using SHA-384 and MGF1 with SHA-384
- PS512: RSASSA-PSS using SHA-512 and MGF1 with SHA-512

Change-Id: Iafc7c60ccb36f4681053dbeb4147bac01b9d724d
Signed-off-by: Donald Chan <donachan@tesla.com>

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Merge "fix(handoff): correct representation of tag_id" into integration

Merge "feat(rme): build TF-A with ENABLE_RME for Armv9.2" into integration

Merge "fix(cm): remove ENABLE_FEAT_MTE usage" into integration

Merge "fix(build): wrap toolchain paths in double quotes" into integration

refactor(arm): replace hard-coded HW_CONFIG DT size

Ensure consistency across all Arm platforms, even those that may already
have an existing macro for this purpose.

Change-Id: I07cd4cfcacf2c991717

refactor(arm): replace hard-coded HW_CONFIG DT size

Ensure consistency across all Arm platforms, even those that may already
have an existing macro for this purpose.

Change-Id: I07cd4cfcacf2c991717f4c115cb0babd2c614d6f
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(cm): remove ENABLE_FEAT_MTE usage

commit@c282384dbb45b6185b4aba14efebbad110d18e49
removed ENABLE_FEAT_MTE but missed its usage in
context structure declaration path.

All mte regs that are curre

fix(cm): remove ENABLE_FEAT_MTE usage

commit@c282384dbb45b6185b4aba14efebbad110d18e49
removed ENABLE_FEAT_MTE but missed its usage in
context structure declaration path.

All mte regs that are currently context saved/restored
are needed only when FEAT_MTE2 is enabled, so move to
usage of FEAT_MTE2 and remove FEAT_MTE usage

Change-Id: I6b4417485fa6b7f52a31045562600945e48e81b7
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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fix(build): wrap toolchain paths in double quotes

Fix issue with Windows paths containing spaces. Recent toolchain
refactoring (cc277de) caused a regression in the Windows build. Ensure
toolchain pa

fix(build): wrap toolchain paths in double quotes

Fix issue with Windows paths containing spaces. Recent toolchain
refactoring (cc277de) caused a regression in the Windows build. Ensure
toolchain path utilities wrap paths in double quoted strings.

Change-Id: I7a136e459d85cff1e9851aedf0a5272a841df09c
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Signed-off-by: Chris Kay <chris.kay@arm.com>
Co-authored-by: Chris Kay <chris.kay@arm.com>

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Merge "docs: clarify build environment prerequisites" into integration

fix(bl1): add missing `__RW_{START,END}__` symbols

These symbols are missing from BL1, which causes undefined reference
errors when linking with LTO enabled.

Change-Id: Id3eda0550c957f5ef0535f0de4f

fix(bl1): add missing `__RW_{START,END}__` symbols

These symbols are missing from BL1, which causes undefined reference
errors when linking with LTO enabled.

Change-Id: Id3eda0550c957f5ef0535f0de4ff2ad87c93b82a
Signed-off-by: Chris Kay <chris.kay@arm.com>

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fix(fvp): don't check MPIDRs with the power controller in BL1

The core platform layer requires an implementation for the
`plat_core_pos_by_mpidr` function. This implementation is currently
missing i

fix(fvp): don't check MPIDRs with the power controller in BL1

The core platform layer requires an implementation for the
`plat_core_pos_by_mpidr` function. This implementation is currently
missing in BL1, which causes undefined reference errors when linking
with LTO.

The FVP platform source file providing this implementation is the
`fvp_topology.c` file, so this change adds it to the BL1 sources for the
FVP.

However, the implementation of this function reaches out to the FVP
power controller driver - `fvp_pm.c` - to validate the MPIDR, and this
file has at least two other dependencies:

- `spe.c`
- `arm_gicvX.c`

Pulling these in correctly is no simple job, so I am simply removing the
power controller validation in BL1 builds.

Change-Id: I56ddf1d799f5fe7f5b0fb2b046f7fe8232b07b27
Signed-off-by: Chris Kay <chris.kay@arm.com>

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fix(arm): only expose `arm_bl2_dyn_cfg_init` to BL2

The `arm_bl2_dyn_cfg_init` function is intended exclusively for BL2 - it
should not be compiled for any other bootloader image. This change hides

fix(arm): only expose `arm_bl2_dyn_cfg_init` to BL2

The `arm_bl2_dyn_cfg_init` function is intended exclusively for BL2 - it
should not be compiled for any other bootloader image. This change hides
it for all but BL2.

Change-Id: I9fa95094dcc30f9fa4cc7bc5b3119ceae82df1ea
Signed-off-by: Chris Kay <chris.kay@arm.com>

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fix(cm): hide `cm_init_context_by_index` from BL1

BL1 requires the context management library but does not use or
implement `cm_init_context_by_index`. This change ensures that is not
compiled into

fix(cm): hide `cm_init_context_by_index` from BL1

BL1 requires the context management library but does not use or
implement `cm_init_context_by_index`. This change ensures that is not
compiled into BL1, as linking with LTO enabled causes an undefined
reference for this function.

Change-Id: I4a4602843bd75bc4f47b3e0c4c5a6efce1514ef6
Signed-off-by: Chris Kay <chris.kay@arm.com>

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fix(bl1): add missing spinlock dependency

The spinlock functions from `spinlock.S` are used by `errata_report.c`,
which is pulled into BL1. In a normal build it appears that this
function call under

fix(bl1): add missing spinlock dependency

The spinlock functions from `spinlock.S` are used by `errata_report.c`,
which is pulled into BL1. In a normal build it appears that this
function call undergoes dead code elimination so the link error is not
reported, but when compiled with LTO enabled the linker reports an
undefined reference.

Change-Id: Id22ffa8c0c8d3ca4b4cd46f0f4aefa53907c8de5
Signed-off-by: Chris Kay <chris.kay@arm.com>

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fix(cpus): workaround for Cortex-A715 erratum 2728106

Cortex-A715 erratum 2728106 is a Cat B(rare) erratum that is present
in revision r0p0, r1p0 and r1p1. It is fixed in r1p2.

The workaround is to

fix(cpus): workaround for Cortex-A715 erratum 2728106

Cortex-A715 erratum 2728106 is a Cat B(rare) erratum that is present
in revision r0p0, r1p0 and r1p1. It is fixed in r1p2.

The workaround is to execute an implementation specific sequence in
the CPU.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2148827/latest

Change-Id: Ic825f9942e7eb13893fdbb44a2090b897758cbc4
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

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Merge "fix(cc): code coverage optimization fix" into integration

Merge "feat(build): redirect stdin to nul during toolchain detection" into integration

docs(build): update GCC to 13.2.Rel1 version

Updating toolchain to the latest production release version
13.2.Rel1 publicly available on:
https://developer.arm.com/downloads/-/arm-gnu-toolchain-down

docs(build): update GCC to 13.2.Rel1 version

Updating toolchain to the latest production release version
13.2.Rel1 publicly available on:
https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads

We build TF-A in CI using x86_64 Linux hosted cross toolchains:
---------------------------------------------------------------
* AArch32 bare-metal target (arm-none-eabi)
* AArch64 bare-metal target (aarch64-none-elf)

Change-Id: I9b60728bcb1a48508ccd4fcbe0114b3029509a64
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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