fix(cm): add more feature registers to EL1 context mgmt

The following system registers are made part of save and restore
operations for EL1 context:

TRFCR_EL1
SCXTNUM_EL0
SCXTNUM_EL1
GCSCR_EL1
GCSC

fix(cm): add more feature registers to EL1 context mgmt

The following system registers are made part of save and restore
operations for EL1 context:

TRFCR_EL1
SCXTNUM_EL0
SCXTNUM_EL1
GCSCR_EL1
GCSCRE0_EL1
GCSPR_EL1
GCSPR_EL0

Change-Id: I1077112bdc29a6c9cd39b9707d6cf10b95fa15e3
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge "fix(spm): add device-regions used in tf-a-tests" into integration

Merge "fix(pmu): fix breakage on ARMv7 CPUs with SP_min as BL32" into integration

Merge "fix(gpt): declare gpt_tlbi_by_pa_ll()" into integration

fix(spm): add device-regions used in tf-a-tests

Device memory region specified in an SP manifest are now validated
against the device memory defined in the SPMC manifest. Therefore
we need to add th

fix(spm): add device-regions used in tf-a-tests

Device memory region specified in an SP manifest are now validated
against the device memory defined in the SPMC manifest. Therefore
we need to add the device memory used in the tf-a-tests to the SPMC
manifests.

Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Change-Id: I47376e67c700705d12338d7078292618a15d5546

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fix(gpt): declare gpt_tlbi_by_pa_ll()

The patch 8754cc5 accidentally removes the declaration of
gpt_tlbi_by_pa_ll() and hence breaks RME builds. This patch
fixes the same.

signed-off-by: Soby Mathe

fix(gpt): declare gpt_tlbi_by_pa_ll()

The patch 8754cc5 accidentally removes the declaration of
gpt_tlbi_by_pa_ll() and hence breaks RME builds. This patch
fixes the same.

signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: I2523982fc48bca2a1f1a36fd9bd3803b01c6916a

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fix(xilinx): check proc variable before use

Check return value from pm_get_proc() to make sure that CPU is valid.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: If51b5d42ce87f31fd732

fix(xilinx): check proc variable before use

Check return value from pm_get_proc() to make sure that CPU is valid.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: If51b5d42ce87f31fd732ab58ae8fcd0e2db0a2a8

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docs(plat): remove TC1 entry from the deprecation table

Since the TC1 platform has been eliminated from the TF-A source code
and CI script repository, updated the deprecation table to remove its
ent

docs(plat): remove TC1 entry from the deprecation table

Since the TC1 platform has been eliminated from the TF-A source code
and CI script repository, updated the deprecation table to remove its
entry.

Change-Id: I93ae03e1f810666e9a6d0c6172a322ff1e960c71
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge changes Ic40e1b7a,I0398b550,Ife594ed6,I3eb0f29b into integration

* changes:
fix(gpt): unify logging messages
chore(gpt): remove gpt_ prefix
feat(aarch64): add functions for TLBI RPALOS

Merge changes Ic40e1b7a,I0398b550,Ife594ed6,I3eb0f29b into integration

* changes:
fix(gpt): unify logging messages
chore(gpt): remove gpt_ prefix
feat(aarch64): add functions for TLBI RPALOS
feat(locks): add bitlock

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fix(cpus): workaround for Cortex-X4 erratum 2740089

Cortex-X4 erratum 2740089 is a Cat B erratum that applies to
all revisions <=r0p1 and is fixed in r0p2. The workaround is to
insert a dsb before t

fix(cpus): workaround for Cortex-X4 erratum 2740089

Cortex-X4 erratum 2740089 is a Cat B erratum that applies to
all revisions <=r0p1 and is fixed in r0p2. The workaround is to
insert a dsb before the isb in the power down sequence.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2432808/latest

Change-Id: I1d0fa4dd383437044a4467591f65a4a8514cabdc
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

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Merge "fix(docs): typo in the romlib design" into integration

Merge "docs: decrease the minimum supported OpenSSL" into integration

fix(docs): typo in the romlib design

There's a typo in the romlib design document when referring to
the generator script. It should be romlib_generator.py instead
of romlib_generate.py so fixed this

fix(docs): typo in the romlib design

There's a typo in the romlib design document when referring to
the generator script. It should be romlib_generator.py instead
of romlib_generate.py so fixed this typo.

Change-Id: I6db7ee66b13c2b0b9d8511da7e0d1b058366281b
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(qemu): allow ARM_ARCH_MAJOR/MINOR override

An upcoming change to the RME support code will use atomic instructions
introduced in Armv8.1 in order to implement bitlocks. In order to do
this, the

feat(qemu): allow ARM_ARCH_MAJOR/MINOR override

An upcoming change to the RME support code will use atomic instructions
introduced in Armv8.1 in order to implement bitlocks. In order to do
this, the code needs to be built with appropriate -march compiler flag
(otherwise the assembler complains about invalid instructions). One way
to do this is specifying ARM_ARCH_MAJOR/MINOR version greater than 8.0,
which is what the main Makefile does when ENABLE_RME is set.

Allow the main Makefile to override the ARM_ARCH_MAJOR/MINOR variables
on the QEMU platform, so that it can also build the bitlock functions.

This only affects firmware built with ENABLE_RME, which is an
experimental feature both in TF-A and QEMU. The QEMU platform code
doesn't support booting an ENABLE_RME firmware on non-RME CPUs at the
moment.

As a result of this change, when ENABLE_RME is set,
make_helpers/arch_features.mk sets ENABLE_TRF_FOR_NS to 1, which needs
to be overridden by the QEMU Makefile.

Change-Id: I695fc98b21d07f6c84003d9e36a57cad2a3c806e
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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Merge "fix: static checks on spmc dts" into integration

fix: static checks on spmc dts

Change the header of the license to have 2024, and
replace spaces for a tab.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: If98161ad35e1ead30e1e0d3ddb4cc6348

fix: static checks on spmc dts

Change the header of the license to have 2024, and
replace spaces for a tab.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: If98161ad35e1ead30e1e0d3ddb4cc6348e83d6ee

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fix(gpt): unify logging messages

This patch modifies GPT library comments and makes
logging messages consistent with PRIx64 usage and
TF-A format used in other modules.
Minor changes are made to mak

fix(gpt): unify logging messages

This patch modifies GPT library comments and makes
logging messages consistent with PRIx64 usage and
TF-A format used in other modules.
Minor changes are made to make the code compliant
with MISRA C requirements.

Change-Id: Ic40e1b7ac43cd9602819698d00e1ce3a8c7183ce
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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chore(gpt): remove gpt_ prefix

This patch removes 'gpt_' prefix from the
names of static functions for better code
readability.

Change-Id: I0398b55047a73209da598b708240fcba47c779f7
Signed-off-by: A

chore(gpt): remove gpt_ prefix

This patch removes 'gpt_' prefix from the
names of static functions for better code
readability.

Change-Id: I0398b55047a73209da598b708240fcba47c779f7
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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feat(aarch64): add functions for TLBI RPALOS

This patch adds tlbirpalos_XYZ() functions to support
TLBI RPALOS instructions for the 4KB-512MB invalidation
range.

Change-Id: Ife594ed6c746d356b4b1fdf

feat(aarch64): add functions for TLBI RPALOS

This patch adds tlbirpalos_XYZ() functions to support
TLBI RPALOS instructions for the 4KB-512MB invalidation
range.

Change-Id: Ife594ed6c746d356b4b1fdf97001a0fe2b5e8cd0
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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fix(cert-create): add guardrails around brainpool usage

OpenSSL has brainpool support only since version 1.1.0, make sure we
put a proper guardrail around it.

Change-Id: Ia2ee686904ed80699f77b1da95

fix(cert-create): add guardrails around brainpool usage

OpenSSL has brainpool support only since version 1.1.0, make sure we
put a proper guardrail around it.

Change-Id: Ia2ee686904ed80699f77b1da953546ab7538ec37
Signed-off-by: Donald Chan <donachan@tesla.com>

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feat(intel): add QSPI get devinfo mailbox cmd

Linux RSU receive QSPI device info from SDM and report to user about
the device info.

Change-Id: Ib41692c9c4888c745a48a0609396aef0ca7fe25b
Signed-off-b

feat(intel): add QSPI get devinfo mailbox cmd

Linux RSU receive QSPI device info from SDM and report to user about
the device info.

Change-Id: Ib41692c9c4888c745a48a0609396aef0ca7fe25b
Signed-off-by: Kah Jing Lee <kah.jing.lee@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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Merge "fix(gicv2): fix SGIR_NSATT bitshift" into integration

Merge changes from topic "lto-fixes" into integration

* changes:
fix(bl1): add missing `__RW_{START,END}__` symbols
fix(fvp): don't check MPIDRs with the power controller in BL1
fix(arm): only

Merge changes from topic "lto-fixes" into integration

* changes:
fix(bl1): add missing `__RW_{START,END}__` symbols
fix(fvp): don't check MPIDRs with the power controller in BL1
fix(arm): only expose `arm_bl2_dyn_cfg_init` to BL2
fix(cm): hide `cm_init_context_by_index` from BL1
fix(bl1): add missing spinlock dependency

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Merge changes from topic "hm/handoff" into integration

* changes:
refactor(fvp): reduce max size of HW_CONFIG to 16KB
refactor(arm): replace hard-coded HW_CONFIG DT size

docs: decrease the minimum supported OpenSSL

Our code does not preclude the use of versions 1.0.x of OpenSSL.
Instead, we discourage it's use due to security concerns. Update the
documentation to re

docs: decrease the minimum supported OpenSSL

Our code does not preclude the use of versions 1.0.x of OpenSSL.
Instead, we discourage it's use due to security concerns. Update the
documentation to reflect this.

Change-Id: I5c60907337f10b05d5c43b0384247c5d4135db50
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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