1/* 2 * Copyright (c) 2020-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/* If SCMI power domain control is enabled */ 8#if TC_SCMI_PD_CTRL_EN 9#define GPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 1) 10#define DPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 2) 11#endif /* TC_SCMI_PD_CTRL_EN */ 12 13/* Use SCMI controlled clocks */ 14#if TC_DPU_USE_SCMI_CLK 15#define DPU_CLK_ATTR1 \ 16 clocks = <&scmi_clk 0>; \ 17 clock-names = "aclk" 18 19#define DPU_CLK_ATTR2 \ 20 clocks = <&scmi_clk 1>; \ 21 clock-names = "pxclk" 22 23#define DPU_CLK_ATTR3 \ 24 clocks = <&scmi_clk 2>; \ 25 clock-names = "pxclk" \ 26/* Use fixed clocks */ 27#else /* !TC_DPU_USE_SCMI_CLK */ 28#define DPU_CLK_ATTR1 \ 29 clocks = <&dpu_aclk>; \ 30 clock-names = "aclk" 31 32#define DPU_CLK_ATTR2 \ 33 clocks = <&dpu_pixel_clk>, <&dpu_aclk>; \ 34 clock-names = "pxclk", "aclk" 35 36#define DPU_CLK_ATTR3 DPU_CLK_ATTR2 37#endif /* !TC_DPU_USE_SCMI_CLK */ 38 39/ { 40 compatible = "arm,tc"; 41 interrupt-parent = <&gic>; 42 #address-cells = <2>; 43 #size-cells = <2>; 44 45 aliases { 46 serial0 = &os_uart; 47 }; 48 49 chosen { 50 /* 51 * Add some dummy entropy for Linux so it 52 * doesn't delay the boot waiting for it. 53 */ 54 rng-seed = <0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 55 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 56 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 57 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 58 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 59 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 60 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 61 0x01 0x02 0x04 0x05 0x06 0x07 0x08 >; 62 }; 63 64 cpus { 65 #address-cells = <1>; 66 #size-cells = <0>; 67 68 cpu-map { 69 cluster0 { 70 core0 { 71 cpu = <&CPU0>; 72 }; 73 core1 { 74 cpu = <&CPU1>; 75 }; 76 core2 { 77 cpu = <&CPU2>; 78 }; 79 core3 { 80 cpu = <&CPU3>; 81 }; 82 core4 { 83 cpu = <&CPU4>; 84 }; 85 core5 { 86 cpu = <&CPU5>; 87 }; 88 core6 { 89 cpu = <&CPU6>; 90 }; 91 core7 { 92 cpu = <&CPU7>; 93 }; 94 }; 95 }; 96 97 /* 98 * The timings below are just to demonstrate working cpuidle. 99 * These values may be inaccurate. 100 */ 101 idle-states { 102 entry-method = "psci"; 103 104 CPU_SLEEP_0: cpu-sleep-0 { 105 compatible = "arm,idle-state"; 106 arm,psci-suspend-param = <0x0010000>; 107 local-timer-stop; 108 entry-latency-us = <300>; 109 exit-latency-us = <1200>; 110 min-residency-us = <2000>; 111 }; 112 CLUSTER_SLEEP_0: cluster-sleep-0 { 113 compatible = "arm,idle-state"; 114 arm,psci-suspend-param = <0x1010000>; 115 local-timer-stop; 116 entry-latency-us = <400>; 117 exit-latency-us = <1200>; 118 min-residency-us = <2500>; 119 }; 120 }; 121 122 amus { 123 amu: amu-0 { 124 #address-cells = <1>; 125 #size-cells = <0>; 126 127 mpmm_gear0: counter@0 { 128 reg = <0>; 129 enable-at-el3; 130 }; 131 132 mpmm_gear1: counter@1 { 133 reg = <1>; 134 enable-at-el3; 135 }; 136 137 mpmm_gear2: counter@2 { 138 reg = <2>; 139 enable-at-el3; 140 }; 141 }; 142 }; 143 144 CPU0:cpu@0 { 145 device_type = "cpu"; 146 compatible = "arm,armv8"; 147 reg = <0x0>; 148 enable-method = "psci"; 149 clocks = <&scmi_dvfs 0>; 150 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 151 capacity-dmips-mhz = <LIT_CAPACITY>; 152 amu = <&amu>; 153 supports-mpmm; 154 }; 155 156 CPU1:cpu@100 { 157 device_type = "cpu"; 158 compatible = "arm,armv8"; 159 reg = <0x100>; 160 enable-method = "psci"; 161 clocks = <&scmi_dvfs 0>; 162 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 163 capacity-dmips-mhz = <LIT_CAPACITY>; 164 amu = <&amu>; 165 supports-mpmm; 166 }; 167 168 CPU2:cpu@200 { 169 device_type = "cpu"; 170 compatible = "arm,armv8"; 171 reg = <0x200>; 172 enable-method = "psci"; 173 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 174 amu = <&amu>; 175 supports-mpmm; 176 }; 177 178 CPU3:cpu@300 { 179 device_type = "cpu"; 180 compatible = "arm,armv8"; 181 reg = <0x300>; 182 enable-method = "psci"; 183 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 184 amu = <&amu>; 185 supports-mpmm; 186 }; 187 188 CPU4:cpu@400 { 189 device_type = "cpu"; 190 compatible = "arm,armv8"; 191 reg = <0x400>; 192 enable-method = "psci"; 193 clocks = <&scmi_dvfs 1>; 194 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 195 capacity-dmips-mhz = <MID_CAPACITY>; 196 amu = <&amu>; 197 supports-mpmm; 198 }; 199 200 CPU5:cpu@500 { 201 device_type = "cpu"; 202 compatible = "arm,armv8"; 203 reg = <0x500>; 204 enable-method = "psci"; 205 clocks = <&scmi_dvfs 1>; 206 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 207 capacity-dmips-mhz = <MID_CAPACITY>; 208 amu = <&amu>; 209 supports-mpmm; 210 }; 211 212 CPU6:cpu@600 { 213 device_type = "cpu"; 214 compatible = "arm,armv8"; 215 reg = <0x600>; 216 enable-method = "psci"; 217 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 218 amu = <&amu>; 219 supports-mpmm; 220 }; 221 222 CPU7:cpu@700 { 223 device_type = "cpu"; 224 compatible = "arm,armv8"; 225 reg = <0x700>; 226 enable-method = "psci"; 227 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 228 amu = <&amu>; 229 supports-mpmm; 230 }; 231 }; 232 233 reserved-memory { 234 #address-cells = <2>; 235 #size-cells = <2>; 236 ranges; 237 238 linux,cma { 239 compatible = "shared-dma-pool"; 240 reusable; 241 size = <0x0 0x8000000>; 242 linux,cma-default; 243 }; 244 245 optee { 246 compatible = "restricted-dma-pool"; 247 reg = <0x0 TC_NS_OPTEE_BASE 0x0 TC_NS_OPTEE_SIZE>; 248 }; 249 250 fwu_mm { 251 reg = <0x0 TC_NS_FWU_BASE 0x0 TC_NS_FWU_SIZE>; 252 no-map; 253 }; 254 }; 255 256 memory { 257 device_type = "memory"; 258 reg = <0x0 TC_NS_DRAM1_BASE 0x0 TC_NS_DRAM1_SIZE>, 259 <HI(PLAT_ARM_DRAM2_BASE) LO(PLAT_ARM_DRAM2_BASE) 260 HI(TC_NS_DRAM2_SIZE) LO(TC_NS_DRAM2_SIZE)>; 261 }; 262 263 psci { 264 compatible = "arm,psci-1.0", "arm,psci-0.2"; 265 method = "smc"; 266 }; 267 268 cpu-pmu { 269 compatible = "arm,armv8-pmuv3"; 270 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 271 }; 272 273 sram: sram@6000000 { 274 compatible = "mmio-sram"; 275 reg = <0x0 PLAT_ARM_NSRAM_BASE 0x0 PLAT_ARM_NSRAM_SIZE>; 276 277 #address-cells = <1>; 278 #size-cells = <1>; 279 ranges = <0 0x0 PLAT_ARM_NSRAM_BASE PLAT_ARM_NSRAM_SIZE>; 280 281 cpu_scp_scmi_mem: scp-shmem@0 { 282 compatible = "arm,scmi-shmem"; 283 reg = <0x0 0x80>; 284 }; 285 }; 286 287 mbox_db_rx: mhu@MHU_RX_ADDR { 288 compatible = "arm,mhuv2-rx","arm,primecell"; 289 reg = <0x0 ADDRESSIFY(MHU_RX_ADDR) 0x0 0x1000>; 290 clocks = <&soc_refclk>; 291 clock-names = "apb_pclk"; 292 #mbox-cells = <2>; 293 interrupts = <GIC_SPI INT_MBOX_RX IRQ_TYPE_LEVEL_HIGH>; 294 interrupt-names = "mhu_rx"; 295 }; 296 297 mbox_db_tx: mhu@MHU_TX_ADDR { 298 compatible = "arm,mhuv2-tx","arm,primecell"; 299 reg = <0x0 ADDRESSIFY(MHU_TX_ADDR) 0x0 0x1000>; 300 clocks = <&soc_refclk>; 301 clock-names = "apb_pclk"; 302 #mbox-cells = <2>; 303 interrupt-names = "mhu_tx"; 304 }; 305 306 firmware { 307 scmi { 308 compatible = "arm,scmi"; 309 mbox-names = "tx", "rx"; 310 mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0 >; 311 shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 315#if TC_SCMI_PD_CTRL_EN 316 scmi_devpd: protocol@11 { 317 reg = <0x11>; 318 #power-domain-cells = <1>; 319 }; 320#endif /* TC_SCMI_PD_CTRL_EN */ 321 322 scmi_dvfs: protocol@13 { 323 reg = <0x13>; 324 #clock-cells = <1>; 325 }; 326 327 scmi_clk: protocol@14 { 328 reg = <0x14>; 329 #clock-cells = <1>; 330 }; 331 }; 332 }; 333 334 gic: interrupt-controller@GIC_CTRL_ADDR { 335 compatible = "arm,gic-v3"; 336 #address-cells = <2>; 337 #interrupt-cells = <3>; 338 #size-cells = <2>; 339 ranges; 340 interrupt-controller; 341 reg = <0x0 0x30000000 0 0x10000>, /* GICD */ 342 <0x0 0x30080000 0 GIC_GICR_OFFSET>; /* GICR */ 343 interrupts = <GIC_PPI 0x9 IRQ_TYPE_LEVEL_LOW>; 344 }; 345 346 timer { 347 compatible = "arm,armv8-timer"; 348 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 349 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 350 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 351 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 352 }; 353 354 soc_refclk: refclk { 355 compatible = "fixed-clock"; 356 #clock-cells = <0>; 357 clock-frequency = <1000000000>; 358 clock-output-names = "apb_pclk"; 359 }; 360 361 soc_refclk60mhz: refclk60mhz { 362 compatible = "fixed-clock"; 363 #clock-cells = <0>; 364 clock-frequency = <60000000>; 365 clock-output-names = "iofpga_clk"; 366 }; 367 368 soc_uartclk: uartclk { 369 compatible = "fixed-clock"; 370 #clock-cells = <0>; 371 clock-frequency = <UARTCLK_FREQ>; 372 clock-output-names = "uartclk"; 373 }; 374 375 /* soc_uart0 on FPGA, ap_ns_uart on FVP */ 376 os_uart: serial@2a400000 { 377 compatible = "arm,pl011", "arm,primecell"; 378 reg = <0x0 0x2A400000 0x0 UART_OFFSET>; 379 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 380 clocks = <&soc_uartclk>, <&soc_refclk>; 381 clock-names = "uartclk", "apb_pclk"; 382 status = "okay"; 383 }; 384 385#if !TC_DPU_USE_SCMI_CLK 386 dpu_aclk: dpu_aclk { 387 compatible = "fixed-clock"; 388 #clock-cells = <0>; 389 clock-frequency = <VENCODER_TIMING_CLK>; 390 clock-output-names = "fpga:dpu_aclk"; 391 }; 392 393 dpu_pixel_clk: dpu-pixel-clk { 394 compatible = "fixed-clock"; 395 #clock-cells = <0>; 396 clock-frequency = <VENCODER_TIMING_CLK>; 397 clock-output-names = "pxclk"; 398 }; 399#endif /* !TC_DPU_USE_SCMI_CLK */ 400 401 vencoder { 402 compatible = "drm,virtual-encoder"; 403 port { 404 vencoder_in: endpoint { 405 remote-endpoint = <&dp_pl0_out0>; 406 }; 407 }; 408 409 display-timings { 410 timing-panel { 411 VENCODER_TIMING; 412 }; 413 }; 414 415 }; 416 417 ethernet: ethernet@18000000 { 418 reg = <0x0 0x18000000 0x0 0x10000>; 419 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 420 421 reg-io-width = <2>; 422 smsc,irq-push-pull; 423 }; 424 425 bp_clock24mhz: clock24mhz { 426 compatible = "fixed-clock"; 427 #clock-cells = <0>; 428 clock-frequency = <24000000>; 429 clock-output-names = "bp:clock24mhz"; 430 }; 431 432 433 sysreg: sysreg@1c010000 { 434 compatible = "arm,vexpress-sysreg"; 435 reg = <0x0 0x001c010000 0x0 0x1000>; 436 gpio-controller; 437 #gpio-cells = <2>; 438 }; 439 440 fixed_3v3: v2m-3v3 { 441 compatible = "regulator-fixed"; 442 regulator-name = "3V3"; 443 regulator-min-microvolt = <3300000>; 444 regulator-max-microvolt = <3300000>; 445 regulator-always-on; 446 }; 447 448 mmci: mmci@1c050000 { 449 compatible = "arm,pl180", "arm,primecell"; 450 reg = <0x0 0x001c050000 0x0 0x1000>; 451 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 453 wp-gpios = <&sysreg 1 0>; 454 bus-width = <4>; 455 max-frequency = <25000000>; 456 vmmc-supply = <&fixed_3v3>; 457 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; 458 clock-names = "mclk", "apb_pclk"; 459 }; 460 461 gpu_clk: gpu_clk { 462 compatible = "fixed-clock"; 463 #clock-cells = <0>; 464 clock-frequency = <1000000000>; 465 }; 466 467 gpu_core_clk: gpu_core_clk { 468 compatible = "fixed-clock"; 469 #clock-cells = <0>; 470 clock-frequency = <1000000000>; 471 }; 472 473 gpu: gpu@2d000000 { 474 compatible = "arm,mali-midgard"; 475 reg = <0x0 0x2d000000 0x0 0x200000>; 476 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 479 interrupt-names = "JOB", "MMU", "GPU"; 480 clocks = <&gpu_core_clk>; 481 clock-names = "shadercores"; 482#if TC_SCMI_PD_CTRL_EN 483 power-domains = <&scmi_devpd GPU_SCMI_PD_IDX>; 484 scmi-perf-domain = <3>; 485#endif /* TC_SCMI_PD_CTRL_EN */ 486 487#if TC_IOMMU_EN 488 iommus = <&smmu_700 0x200>; 489#endif /* TC_IOMMU_EN */ 490 pbha { 491 int-id-override = <0 0x22>, <2 0x23>, <4 0x23>, <7 0x22>, 492 <8 0x22>, <9 0x22>, <10 0x22>, <11 0x22>, 493 <12 0x22>, <13 0x22>, <16 0x22>, <17 0x32>, 494 <18 0x32>, <19 0x22>, <20 0x22>, <21 0x32>, 495 <22 0x32>, <24 0x22>, <28 0x32>; 496 propagate-bits = <0x0f>; 497 }; 498 }; 499 500 power_model_simple { 501 /* 502 * Numbers used are irrelevant to Titan, 503 * it helps suppressing the kernel warnings. 504 */ 505 compatible = "arm,mali-simple-power-model"; 506 static-coefficient = <2427750>; 507 dynamic-coefficient = <4687>; 508 ts = <20000 2000 (-20) 2>; 509 thermal-zone = ""; 510 }; 511 512#if TC_IOMMU_EN 513 smmu_700: iommu@3f000000 { 514 #iommu-cells = <1>; 515 compatible = "arm,smmu-v3"; 516 reg = <0x0 0x3f000000 0x0 0x5000000>; 517 interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>, 518 <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, 519 <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>; 520 interrupt-names = "eventq", "cmdq-sync", "gerror"; 521 dma-coherent; 522 }; 523#endif /* TC_IOMMU_EN */ 524 525 dp0: display@DPU_ADDR { 526 #address-cells = <1>; 527 #size-cells = <0>; 528 compatible = "arm,mali-d71"; 529 reg = <HI(ADDRESSIFY(DPU_ADDR)) LO(ADDRESSIFY(DPU_ADDR)) 0 0x20000>; 530 interrupts = <GIC_SPI DPU_IRQ IRQ_TYPE_LEVEL_HIGH>; 531 interrupt-names = "DPU"; 532 DPU_CLK_ATTR1; 533#if TC_IOMMU_EN 534 iommus = <&smmu_700 0x100>; 535#endif /* TC_IOMMU_EN */ 536 537 pl0: pipeline@0 { 538 reg = <0>; 539 DPU_CLK_ATTR2; 540 pl_id = <0>; 541 ports { 542 #address-cells = <1>; 543 #size-cells = <0>; 544 port@0 { 545 reg = <0>; 546 dp_pl0_out0: endpoint { 547 remote-endpoint = <&vencoder_in>; 548 }; 549 }; 550 }; 551 }; 552 553 pl1: pipeline@1 { 554 reg = <1>; 555 DPU_CLK_ATTR3; 556 pl_id = <1>; 557 ports { 558 #address-cells = <1>; 559 #size-cells = <0>; 560 port@0 { 561 reg = <0>; 562 }; 563 }; 564 }; 565 }; 566 567 /* 568 * L3 cache in the DSU is the Memory System Component (MSC) 569 * The MPAM registers are accessed through utility bus in the DSU 570 */ 571 msc0 { 572 compatible = "arm,mpam-msc"; 573 reg = <MPAM_ADDR 0x0 0x2000>; 574 }; 575 576 ete0 { 577 compatible = "arm,embedded-trace-extension"; 578 cpu = <&CPU0>; 579 }; 580 581 ete1 { 582 compatible = "arm,embedded-trace-extension"; 583 cpu = <&CPU1>; 584 }; 585 586 ete2 { 587 compatible = "arm,embedded-trace-extension"; 588 cpu = <&CPU2>; 589 }; 590 591 ete3 { 592 compatible = "arm,embedded-trace-extension"; 593 cpu = <&CPU3>; 594 }; 595 596 ete4 { 597 compatible = "arm,embedded-trace-extension"; 598 cpu = <&CPU4>; 599 }; 600 601 ete5 { 602 compatible = "arm,embedded-trace-extension"; 603 cpu = <&CPU5>; 604 }; 605 606 ete6 { 607 compatible = "arm,embedded-trace-extension"; 608 cpu = <&CPU6>; 609 }; 610 611 ete7 { 612 compatible = "arm,embedded-trace-extension"; 613 cpu = <&CPU7>; 614 }; 615 616 trbe { 617 compatible = "arm,trace-buffer-extension"; 618 interrupts = <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>; 619 }; 620 621 trusty { 622 #size-cells = <0x02>; 623 #address-cells = <0x02>; 624 ranges = <0x00>; 625 compatible = "android,trusty-v1"; 626 627 virtio { 628 compatible = "android,trusty-virtio-v1"; 629 }; 630 631 test { 632 compatible = "android,trusty-test-v1"; 633 }; 634 635 log { 636 compatible = "android,trusty-log-v1"; 637 }; 638 639 irq { 640 ipi-range = <0x08 0x0f 0x08>; 641 interrupt-ranges = <0x00 0x0f 0x00 0x10 0x1f 0x01 0x20 0x3f 0x02>; 642 interrupt-templates = <0x01 0x00 0x8001 0x01 0x01 0x04 0x8001 0x01 0x00 0x04>; 643 compatible = "android,trusty-irq-v1"; 644 }; 645 }; 646 647 /* used in U-boot, Linux doesn't care */ 648 arm_ffa { 649 compatible = "arm,ffa"; 650 method = "smc"; 651 }; 652}; 653