| 88ab2261 | 19-Feb-2024 |
Salman Nabi <salman.nabi@arm.com> |
refactor(armada): console runtime switch on bl31 exit
Flush the FIFO before switching to runtime. This is so that there are no lingering chars in the FIFO when we move to the runtime console.
TF-A
refactor(armada): console runtime switch on bl31 exit
Flush the FIFO before switching to runtime. This is so that there are no lingering chars in the FIFO when we move to the runtime console.
TF-A plans to refactor the console_Switch_state(CONSOLE_FLAG_RUNTIME) and console_flush() calls and make them the last calls in bl31_main() (before BL31 exits). Until then they are being left as the last calls in bl31_plat_runtime_setup() for testing before refactoring.
This patch only affects the Armada SoC of Marvell's platform.
Change-Id: I7082fdb8c5507cd1ce5915d67e61e638605982e0 Signed-off-by: Salman Nabi <salman.nabi@arm.com>
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| d3c643c2 | 19-Feb-2024 |
Salman Nabi <salman.nabi@arm.com> |
refactor(imx): console runtime switch on bl31 exit
Flush the FIFO before switching to runtime. This is so that there are no lingering chars in the FIFO when we move to the runtime console.
TF-A pla
refactor(imx): console runtime switch on bl31 exit
Flush the FIFO before switching to runtime. This is so that there are no lingering chars in the FIFO when we move to the runtime console.
TF-A plans to refactor the console_Switch_state(CONSOLE_FLAG_RUNTIME) and console_flush() calls and make them the last calls in bl31_main() (before BL31 exits). Until then they are being left as the last calls in bl31_plat_runtime_setup() for testing before refactoring.
This patch affects the Freescale/NXP SoCs imx93, imx8qm and imx8qx.
Change-Id: Iece74579e1d15eeeb8279db0c53d74bce45545bd Signed-off-by: Salman Nabi <salman.nabi@arm.com>
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| 46163ddd | 19-Feb-2024 |
Salman Nabi <salman.nabi@arm.com> |
refactor(brcm): console runtime switch on bl31 exit
Flush the FIFO before switching to runtime. This is so that there are no lingering chars in the FIFO when we move to the runtime console.
TF-A pl
refactor(brcm): console runtime switch on bl31 exit
Flush the FIFO before switching to runtime. This is so that there are no lingering chars in the FIFO when we move to the runtime console.
TF-A plans to refactor the console_Switch_state(CONSOLE_FLAG_RUNTIME) and console_flush() calls and make them the last calls in bl31_main() (before BL31 exits). Until then they are being left as the last calls in bl31_plat_runtime_setup() for testing before refactoring.
This patch affects the Broadcom platform only.
Change-Id: I693f749bbf56911638b03e069659e86b95b1050e Signed-off-by: Salman Nabi <salman.nabi@arm.com>
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| 2ba0c06c | 08-May-2024 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "docs(maintainers): remove a maintainer for MediaTek SoCs" into integration |
| dd038061 | 08-May-2024 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "fix_psci_osi" into integration
* changes: fix(psci): fix parent_idx in psci_validate_state_coordination fix(psci): mask the Last in Level nibble in StateId |
| 655e62aa | 08-May-2024 |
Ronak Jain <ronak.jain@amd.com> |
fix(xilinx): follow MISRA-C standards for condition check
As per the MISRA-C standards, there should be proc == NULL not just !proc.
Fix the same.
Change-Id: I0e7650c09b045882a0235869d7ef9fca27f96
fix(xilinx): follow MISRA-C standards for condition check
As per the MISRA-C standards, there should be proc == NULL not just !proc.
Fix the same.
Change-Id: I0e7650c09b045882a0235869d7ef9fca27f96d9a Signed-off-by: Ronak Jain <ronak.jain@amd.com>
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| 20fa9fc8 | 08-May-2024 |
Ronak Jain <ronak.jain@amd.com> |
fix(zynqmp): resolve null pointer dereferencing
The upstream coverity tool has reported the null pointer dereferences (NULL_RETURNS) warning.
The coverity warning, Dereferencing a pointer that migh
fix(zynqmp): resolve null pointer dereferencing
The upstream coverity tool has reported the null pointer dereferences (NULL_RETURNS) warning.
The coverity warning, Dereferencing a pointer that might be "NULL" "proc" when calling "pm_client_suspend".
Fix the same by checking the NULL before processing further.
Change-Id: I33acead9250bab0ed24b94aa1c1bdc31e80de771 Signed-off-by: Ronak Jain <ronak.jain@amd.com>
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| 2b67ee6d | 08-May-2024 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "chore: rename hermes to neoverse-n3" into integration |
| 412d92fd | 17-Oct-2023 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
fix(psci): fix parent_idx in psci_validate_state_coordination
Update parent_idx support in psci_validate_state_coordination() as it is done in psci_do_state_coordination(). The modified loop verifie
fix(psci): fix parent_idx in psci_validate_state_coordination
Update parent_idx support in psci_validate_state_coordination() as it is done in psci_do_state_coordination(). The modified loop verifies the targeted state for all the branch up to end_pwrlvl in the topology for the current cpu.
Fixes: 606b7430077c ("feat(psci): add support for OS-initiated mode") Change-Id: I14420f64a18b543eb4e10a1279f51cc17558c13c Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
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| 0a9c244b | 29-Jan-2024 |
Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> |
fix(psci): mask the Last in Level nibble in StateId
In the ARM recommended StateID Encoding, the index for the power level where the calling core is last to go idle use the last niblle of the StateI
fix(psci): mask the Last in Level nibble in StateId
In the ARM recommended StateID Encoding, the index for the power level where the calling core is last to go idle use the last niblle of the StateId.
Even if this nibble is necessary for OS-initiated mode, it can be used by caller even when this OSI mode is not used.
In arm_validate_power_state() function, the StateId is compared with content of arm_pm_idle_states[] build with the arm_make_pwrstate_lvl2 macro, without Last in Level information. So it is safe to mask this nibble for ARM platform in all the cases, and that avoids issues with caller with use the same StateId encoding with OSI mode activated or not (in tftf tests for example, the input(power state) parameter = (0x40001022) and the associated power state is 0x40000022).
Change-Id: I45e8e2b8f526fb61b94cf134d7d4aa3bac4c215d Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
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| 7d009327 | 07-May-2024 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "docs(fvp): restructure FVP platform documentation" into integration |
| 4efd2193 | 30-Oct-2023 |
Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> |
docs(context-mgmt): add documentation for context management library
This patch adds some documentation for the context management library. It mainly covers the design at a higher level, with more f
docs(context-mgmt): add documentation for context management library
This patch adds some documentation for the context management library. It mainly covers the design at a higher level, with more focus on the cold boot and warm boot entries as well as the operations involved during context switch. Further it also includes a section on feature enablement for individual world contexts.
Change-Id: I77005730f4df7f183f56a2c6dd04f6362e813c07 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
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| ee9cfacc | 07-May-2024 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "makefile-cleanup" into integration
* changes: build: improve diagnostics for unrecognized toolchain tools build(rzg): separate BL2 and BL31 SREC generation build(rcar
Merge changes from topic "makefile-cleanup" into integration
* changes: build: improve diagnostics for unrecognized toolchain tools build(rzg): separate BL2 and BL31 SREC generation build(rcar): separate BL2 and BL31 SREC generation build: separate preprocessing from DTB compilation build: remove `MAKE_BUILD_STRINGS` function
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| ba6b6949 | 06-May-2024 |
Govindraj Raja <govindraj.raja@arm.com> |
chore: rename hermes to neoverse-n3
Rename hermes cpu to Neoverse-N3
Change-Id: I912d4c824c5004a8c1909c68fef77f1f5e202b8a Signed-off-by: Govindraj Raja <govindraj.raja@arm.com> |
| 531d923b | 07-May-2024 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "fix(tc): enable FEAT_MTE2" into integration |
| 2a0ca84f | 07-May-2024 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "sm/feat_detect" into integration
* changes: refactor(cpufeat): restore functions in detect_arch_features refactor(cpufeat): add macro to simplify is_feat_xx_present c
Merge changes from topic "sm/feat_detect" into integration
* changes: refactor(cpufeat): restore functions in detect_arch_features refactor(cpufeat): add macro to simplify is_feat_xx_present chore: simplify the macro names in ENABLE_FEAT mechanism
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| 15dfbdfc | 07-May-2024 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "gr/smccc-updates" into integration
* changes: refactor(smccc): refactor vendor-el3 build refactor(docs): added versioning to smccc services feat((smccc): add version
Merge changes from topic "gr/smccc-updates" into integration
* changes: refactor(smccc): refactor vendor-el3 build refactor(docs): added versioning to smccc services feat((smccc): add version FID for PMF refactor(smccc): move pmf to vendor el3 calls refactor(smccc): move debugfs to vendor el3 calls feat(smccc): add vendor-specific el3 service feat(smccc): add vendor specific el3 id
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| 6aa5d1b3 | 07-May-2024 |
Younghyun Park <younghyunpark@google.com> |
feat(cpus): support to update External LLC presence in Neoverse V2
The CPUECTLR_EL1.EXTLLC bit indicates that an external last level cache(LLC) is present in the system. The default value is interna
feat(cpus): support to update External LLC presence in Neoverse V2
The CPUECTLR_EL1.EXTLLC bit indicates that an external last level cache(LLC) is present in the system. The default value is internal LLC. Some systems which may have External LLC can enable the External LLC presece with new build option 'NEOVERSE_Vx_EXTERNAL_LLC'.
Change-Id: I740947f1ef78e31626dc5b96f6d6dc6658d0120f Signed-off-by: Younghyun Park <younghyunpark@google.com>
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| 3c225878 | 01-May-2024 |
Govindraj Raja <govindraj.raja@arm.com> |
refactor(smccc): refactor vendor-el3 build
Currently we are building vendor-specific EL3 by default similar to arm-sip but unfortunately this causes few troubles for now.
- Few model builds configu
refactor(smccc): refactor vendor-el3 build
Currently we are building vendor-specific EL3 by default similar to arm-sip but unfortunately this causes few troubles for now.
- Few model builds configuration like 'fvp-dynamiq-aarch64-only' is on 256KB SRAM border and this configuration is also run on some older models like A710 and N2, so we cant move them to 384KB SRAM size and to new model.
- Not able to move some older model builds to new model due to known issue in power modelling in some of the models, making it difficult to transition.
However vendor-specific EL3 is currently using PMF, DEBUGFS so building the vendor EL3 support only when any of this sub-service is built also helps to avoid bloating BL31 image size in certain configurations.
However this is not end of road, we will monitor how vendor-specific EL3 grows with sub-service and if needed will make this interface to built by default like arm-sip range. Also this doesn't stop platform owners to make vendor-specific EL3 to be enabled by default for their platform configuration.
Change-Id: I23322574bdeb7179441a580ad4f093216a948bbf Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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| 320fb293 | 19-Mar-2024 |
Govindraj Raja <govindraj.raja@arm.com> |
refactor(docs): added versioning to smccc services
With addition of vendor-specific el3 monitor service calls debugfs and pmf are moved from arm-sip to vendor-specific el3 range.
Going forward any
refactor(docs): added versioning to smccc services
With addition of vendor-specific el3 monitor service calls debugfs and pmf are moved from arm-sip to vendor-specific el3 range.
Going forward any changes to SMCCC services can be captured from docs file table.
Use one FID allocated per sub-feature to track changes in sub-feature. Modify top level version only when we break version probing or discovery.
Change-Id: I14ceeab79f29ae57a5d7c523147f6ecaa5574f79 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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| 42cbefc7 | 23-Apr-2024 |
Govindraj Raja <govindraj.raja@arm.com> |
feat((smccc): add version FID for PMF
Introduce a version FID for PMF.
Change-Id: I6b0a7f54aefc2839704e03c5da2243d7c85f8a49 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com> |
| f7679d43 | 15-Apr-2024 |
Govindraj Raja <govindraj.raja@arm.com> |
refactor(smccc): move pmf to vendor el3 calls
Move pmf support to vendor-specific EL3 Monitor Service Calls. Remove pmf call count as it's not supported in vendor-specific el3 as per SMCCC Documenta
refactor(smccc): move pmf to vendor el3 calls
Move pmf support to vendor-specific EL3 Monitor Service Calls. Remove pmf call count as it's not supported in vendor-specific el3 as per SMCCC Documentation 1.5: https://developer.arm.com/documentation/den0028/latest
Add a deprecation notice to inform PMF is moved from arm-sip range to vendor-specific EL3 range. PMF support from arm-sip range will be removed and will not available after TF-A 2.12 release.
Change-Id: Ie1e14aa601d4fc3db352cd5621d842017a18e9ec Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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| 273b8983 | 07-Mar-2024 |
Govindraj Raja <govindraj.raja@arm.com> |
refactor(smccc): move debugfs to vendor el3 calls
Move debugfs to Vendor-Specific EL3 Monitor Service Calls. Function Identifier for Vendor-Specific EL3 Monitor Service is '7' and allocated subrange
refactor(smccc): move debugfs to vendor el3 calls
Move debugfs to Vendor-Specific EL3 Monitor Service Calls. Function Identifier for Vendor-Specific EL3 Monitor Service is '7' and allocated subranges of Function identifiers to different services are:
0x87000000-0x8700FFFF-SMC32: Vendor-Specific EL3 Monitor Service Calls 0xC7000000-0xC700FFFF-SMC64: Vendor-Specific EL3 Monitor Service Calls
Amend Debugfs FID's to use this range and id.
Add a deprecation notice to inform debugfs moved from arm-sip range to Vendor-Specific EL3 range. Debugfs support from arm-sip range will be removed and will not be available after TF-A 2.12 release.
Reference to debugfs component level documentation: https://trustedfirmware-a.readthedocs.io/en/latest/components/debugfs-design.html#overview
Change-Id: I97a50170178f361f70c95ed0049bc4e278de59d7 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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| de6b79d8 | 23-Feb-2024 |
Govindraj Raja <govindraj.raja@arm.com> |
feat(smccc): add vendor-specific el3 service
Add support for vendor-specific el3 service. SMCCC 1.5 introduces support for vendor-specific EL3 monitor calls.
SMCCC Documentation reference: https://
feat(smccc): add vendor-specific el3 service
Add support for vendor-specific el3 service. SMCCC 1.5 introduces support for vendor-specific EL3 monitor calls.
SMCCC Documentation reference: https://developer.arm.com/docs/den0028/latest
Change-Id: Id8bc43842eecdb7a8a2ec7f31a631e88fe4fe0b4 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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| be5b1e22 | 15-Feb-2024 |
Govindraj Raja <govindraj.raja@arm.com> |
feat(smccc): add vendor specific el3 id
Add vendor specific el3 function id and update docs for the same.
SMCCC Documentation reference: https://developer.arm.com/documentation/den0028/latest
Chan
feat(smccc): add vendor specific el3 id
Add vendor specific el3 function id and update docs for the same.
SMCCC Documentation reference: https://developer.arm.com/documentation/den0028/latest
Change-Id: Ieeb63608ad74d7b764d7131d8a92ecf10053c50d Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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