Merge "fix(versal): kernel QEMU boot is failing on versal platform" into integration

Merge "feat(versal): add support for QEMU COSIM platform" into integration

Merge "feat(fvp): scale SP_MIN max size based on SRAM size" into integration

fix(xilinx): warn if reserved memory pre-exists in DT

Memory reservation for tf-a does not happen in
runtime if memory reservation node pre-exists in DT.
Presence of reserved area is checked and use

fix(xilinx): warn if reserved memory pre-exists in DT

Memory reservation for tf-a does not happen in
runtime if memory reservation node pre-exists in DT.
Presence of reserved area is checked and user is
warned if it pre-exists.

Change-Id: I50e18be942777747e9074bb9d8e0305a29c28178
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

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Merge "docs: add load address relative offset node" into integration

Merge "fix(qemu): update rmmd_attest_get_platform_token()" into integration

docs: add load address relative offset node

When this is provided in the partition manifest, it should be added to
the load address to get the base address of the region.

Signed-off-by: Davidson K

docs: add load address relative offset node

When this is provided in the partition manifest, it should be added to
the load address to get the base address of the region.

Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
Change-Id: Ib6d3d6a29af0a3eb87fac67c58220ba25342e1cd

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Merge changes I09ab0a5c,I87d0a492,I613a52ae,I2fcd8d32,Ie91527a7, ... into integration

* changes:
feat(stm32mp2): manage DDR FW via FIP
feat(stm32mp2): introduce DDR type compilation flags
feat

Merge changes I09ab0a5c,I87d0a492,I613a52ae,I2fcd8d32,Ie91527a7, ... into integration

* changes:
feat(stm32mp2): manage DDR FW via FIP
feat(stm32mp2): introduce DDR type compilation flags
feat(stm32mp2): add RISAB registers description
feat(stm32mp2-fdts): add BL31 info in fw-config
feat(stm32mp2): add minimal support for BL31
feat(st): manage BL31 FCONF load_info struct

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feat(versal): add support for QEMU COSIM platform

QEMU COSIM introduces a new platform id for Versal Platform.
QEMU COSIM is equivalent to QEMU with additional COSIM
extensions, so just switching pl

feat(versal): add support for QEMU COSIM platform

QEMU COSIM introduces a new platform id for Versal Platform.
QEMU COSIM is equivalent to QEMU with additional COSIM
extensions, so just switching platform_id to QEMU if QEMU COSIM
id is detected.

Change-Id: If81e0bf04301c7101f89d0df13134f7d04e8c257
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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feat(stm32mp2): manage DDR FW via FIP

This feature is enabled by default using STM32MP_DDR_FIP_IO_STORAGE.

DDR firmware binary is loaded from FIP to SRAM1 which needs to be
mapped.
Only half of the

feat(stm32mp2): manage DDR FW via FIP

This feature is enabled by default using STM32MP_DDR_FIP_IO_STORAGE.

DDR firmware binary is loaded from FIP to SRAM1 which needs to be
mapped.
Only half of the SRAM1 will be allocated to TF-A.
RISAB3 has to be configured to allow access to SRAM1.
Add image ID and update maximum number on platform side also.

Fill related descriptor information, add policy and update numbers.
DDR_TYPE variable is used to identify binary file, and image is now
added in the fiptool command line.

The DDR PHY firmware is not in TF-A repository. It can be found at
https://github.com/STMicroelectronics/stm32-ddr-phy-binary
To ease the selection of the firmware path, STM32MP_DDR_FW_PATH is added
to platform.mk file.

Change-Id: I09ab0a5c63406055a7b5ccd16d65e443de47ca2f
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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feat(stm32mp2): introduce DDR type compilation flags

Binary size limitation implies to define DDR type build flags.
User must set one single type in the build command line.
DDR_TYPE is then deduced,

feat(stm32mp2): introduce DDR type compilation flags

Binary size limitation implies to define DDR type build flags.
User must set one single type in the build command line.
DDR_TYPE is then deduced, and will help in relative definitions.
A check routine is implemented to verify correct configuration.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I87d0a492196efea33831d9c090e6e434cc7c0a1e

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feat(stm32mp2): add RISAB registers description

Describe the RISAB (Resource isolation slave unit for address space
protection (block-based)) peripheral registers.

Change-Id: I613a52ae6d94264137378

feat(stm32mp2): add RISAB registers description

Describe the RISAB (Resource isolation slave unit for address space
protection (block-based)) peripheral registers.

Change-Id: I613a52ae6d94264137378b805119d38ee59ae762
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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feat(stm32mp2-fdts): add BL31 info in fw-config

Add BL31 load address (beginning on SYSRAM) and size in fw-config DT
file.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Maxime Mé

feat(stm32mp2-fdts): add BL31 info in fw-config

Add BL31 load address (beginning on SYSRAM) and size in fw-config DT
file.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I2fcd8d326f394090401ac59b47216d59d3e911bc

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feat(stm32mp2): add minimal support for BL31

Add the required files to compile BL31 on STM32MP2.
Update BL2 configuration to load BL31. The platform boots until BL31,
but stops here as no other bina

feat(stm32mp2): add minimal support for BL31

Add the required files to compile BL31 on STM32MP2.
Update BL2 configuration to load BL31. The platform boots until BL31,
but stops here as no other binaries are loaded as DDR is not
initialized.
At runtime, BL31 will use only the first half of the SYSRAM, the upper
half will be used for non-secure DMA LLIs. To be sure nothing from this
area is still in the cache, invalidate the upper SYSRAM before enabling
BL31 cache. BL31 should then map only first half of the SYSRAM. But it
must temporarily map the upper half read-only, as this is where we will
retrieve BL2 parameters, used to fill registers for next boot stages.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Ie91527a7a26625624b4b3c65fb6a0ca9dd355dbd

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Merge changes from topic "draft-ffm-rats-cca-token-00" into integration

* changes:
refactor(docs): update RSE docs to match the example CCA token
refactor(qemu): use the example CCA platform tok

Merge changes from topic "draft-ffm-rats-cca-token-00" into integration

* changes:
refactor(docs): update RSE docs to match the example CCA token
refactor(qemu): use the example CCA platform token from iat-verifier
refactor(fvp): use the example CCA platform token from iat-verifier

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fix(qemu): update rmmd_attest_get_platform_token()

Update the parameters to rmmd_attest_get_platform_token(), which can now
handle platform tokens larger than 4kB. Since the QEMU sample token is
sma

fix(qemu): update rmmd_attest_get_platform_token()

Update the parameters to rmmd_attest_get_platform_token(), which can now
handle platform tokens larger than 4kB. Since the QEMU sample token is
smaller than 4kB, our implementation remains the same. Take the
opportunity to clean up the function slightly.

Change-Id: Id5a1d576968ebd160d2b79c1f38392d4ecc89421
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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Merge "refactor(rmmd): plat token requests in pieces" into integration

refactor(rmmd): plat token requests in pieces

Until now, the attestation token size was limited by the size of the
shared buffer between RMM and TF-A. With this change, RMM can now
request the token

refactor(rmmd): plat token requests in pieces

Until now, the attestation token size was limited by the size of the
shared buffer between RMM and TF-A. With this change, RMM can now
request the token in pieces, so they fit in the shared buffer. A new
output parameter was added to the SMC call, which will return (along
with the size of bytes copied into the buffer) the number of bytes
of the token that remain to be retrieved.

TF-A will keep an offset variable that will indicate the position in
the token where the next call will retrieve bytes from. This offset
will be increased on every call by adding the number number of bytes
copied. If the received hash size is not 0, TF-A will reset the
offset to 0 and copy from that position on.

The SMC call will now return at most the size of the shared buffer
in bytes on every call. Therefore, from now on, multiple SMC calls
may be needed to be issued if the token size exceeds the shared
buffer size.

Change-Id: I591f7013d06f64e98afaf9535dbea6f815799723
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

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fix(versal): kernel QEMU boot is failing on versal platform

Due to deprecation of VERSAL_PLATFORM build argument,
the board detection is done at runtime due to this the cpu
and uart clock freq was n

fix(versal): kernel QEMU boot is failing on versal platform

Due to deprecation of VERSAL_PLATFORM build argument,
the board detection is done at runtime due to this the cpu
and uart clock freq was not set as required to silicon values.

Updated Versal QEMU cpu_clock and uart_clock to silicon values.

Change-Id: I7c772f07ba45eb7e0ae095fd670718190e24f0d7
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

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refactor(docs): update RSE docs to match the example CCA token

The RSE documentation includes binary and JSON dumps of the CCA platform
token. This change updates those to match the example CCA plat

refactor(docs): update RSE docs to match the example CCA token

The RSE documentation includes binary and JSON dumps of the CCA platform
token. This change updates those to match the example CCA platform
token from [1] and [2], which is also the one returned by the FVP and
QEMU platforms.

[1] https://review.trustedfirmware.org/c/TF-M/tf-m-tools/+/30812
[2] https://review.trustedfirmware.org/c/TF-M/tf-m-tools/+/31036

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Icf91035c5a56c8fa34a7055a969a6ebd8242d460

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refactor(qemu): use the example CCA platform token from iat-verifier

In [1] and [2], the example CCA platform token has been updated to be
aligned with the new profile(s) defined in draft-ffm-rats-c

refactor(qemu): use the example CCA platform token from iat-verifier

In [1] and [2], the example CCA platform token has been updated to be
aligned with the new profile(s) defined in draft-ffm-rats-cca-token-00.

This change replaces the static CCA platform token in QEMU.

[1] https://review.trustedfirmware.org/c/TF-M/tf-m-tools/+/30812
[2] https://review.trustedfirmware.org/c/TF-M/tf-m-tools/+/31036

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I9153df1e6c1be81e669d5495dbe8d1a52e86cdff

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refactor(fvp): use the example CCA platform token from iat-verifier

In [1] and [2], the example CCA platform token has been updated to be
aligned with the new profile(s) defined in draft-ffm-rats-cc

refactor(fvp): use the example CCA platform token from iat-verifier

In [1] and [2], the example CCA platform token has been updated to be
aligned with the new profile(s) defined in draft-ffm-rats-cca-token-00.

This change replaces the static CCA platform token in the FVP platform.

[1] https://review.trustedfirmware.org/c/TF-M/tf-m-tools/+/30812
[2] https://review.trustedfirmware.org/c/TF-M/tf-m-tools/+/31036

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Ia23f0dffe618dca04f9f3c46c953a6f021101b09

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Merge "fix(fvp): enable FEAT_MTE2" into integration

Merge "fix(mte): improve ENABLE_FEAT_MTE deprecation warning" into integration

fix(fvp): enable FEAT_MTE2

ENABLE_FEAT_MTE2 controls the trapping of some MTE related system
registers. If the memory_tagging_support_level parameter on the FVP
command line is set to higher values,

fix(fvp): enable FEAT_MTE2

ENABLE_FEAT_MTE2 controls the trapping of some MTE related system
registers. If the memory_tagging_support_level parameter on the FVP
command line is set to higher values, non-secure world will see the
feature bits in the CPU ID registers and will use those registers,
triggering a panic in BL31.

Enable the feature in the optional form for the FVP build, to avoid any
panics.

Change-Id: I26ba444d784adf165db81048f93e11361c7f11ac
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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