fix(tc): define status to fix SPM tests

The failure was caused by missing a variable definition, `status`
in the RSE initialisation patch.

Change-Id: I937a39e20fae39f3a6d14fe66af578c166545301
Signe

fix(tc): define status to fix SPM tests

The failure was caused by missing a variable definition, `status`
in the RSE initialisation patch.

Change-Id: I937a39e20fae39f3a6d14fe66af578c166545301
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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fix(el3-spmc): move ERROR line inside conditional

Fix an issue where one ERROR line was placed
incorrectly outside its conditional check.

Signed-off-by: Andrei Homescu <ahomescu@google.com>
Change-

fix(el3-spmc): move ERROR line inside conditional

Fix an issue where one ERROR line was placed
incorrectly outside its conditional check.

Signed-off-by: Andrei Homescu <ahomescu@google.com>
Change-Id: I7860c399e4a84de6eaa4139fe2103595c52576dd

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fix(cpus): workaround for CVE-2024-5660 for Cortex-X925

Implements mitigation for CVE-2024-5660 that affects Cortex-X925
revisions r0p0, r0p1.
The workaround is to disable the hardware page aggregat

fix(cpus): workaround for CVE-2024-5660 for Cortex-X925

Implements mitigation for CVE-2024-5660 that affects Cortex-X925
revisions r0p0, r0p1.
The workaround is to disable the hardware page aggregation at
EL3 by setting CPUECTLR_EL1[46] = 1'b1.

Public Documentation:
https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-5660

Change-Id: I9d5a07ca6b89b27d8876f4349eff2af26c962d8a
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(cpus): workaround for CVE-2024-5660 for Cortex-X2

Implements mitigation for CVE-2024-5660 that affects Cortex-X2
revisions r0p0, r1p0, r2p0, r2p1.
The workaround is to disable the hardware page

fix(cpus): workaround for CVE-2024-5660 for Cortex-X2

Implements mitigation for CVE-2024-5660 that affects Cortex-X2
revisions r0p0, r1p0, r2p0, r2p1.
The workaround is to disable the hardware page aggregation at
EL3 by setting CPUECTLR_EL1[46] = 1'b1

Public Documentation:
https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-5660

Change-Id: If28804e154617a39d7d52c40b3a00a14a39df929
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(cpus): workaround for CVE-2024-5660 for Cortex-A77

Implements mitigation for CVE-2024-5660 that affects Cortex-A77
revisions r0p0, r1p0, r1p1.
The workaround is to disable the hardware page aggr

fix(cpus): workaround for CVE-2024-5660 for Cortex-A77

Implements mitigation for CVE-2024-5660 that affects Cortex-A77
revisions r0p0, r1p0, r1p1.
The workaround is to disable the hardware page aggregation at
EL3 by setting CPUECTLR_EL1[46] = 1'b1.

Public Documentation:
https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-5660

Change-Id: Ic71b163883ea624e9f2f77deb8b30c69612938b9
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(cpus): workaround for CVE-2024-5660 for Neoverse-V1

Implements mitigation for CVE-2024-5660 that affects Neoverse-V1
revisions r0p0, r1p0, r1p1, r1p2.
The workaround is to disable the hardware p

fix(cpus): workaround for CVE-2024-5660 for Neoverse-V1

Implements mitigation for CVE-2024-5660 that affects Neoverse-V1
revisions r0p0, r1p0, r1p1, r1p2.
The workaround is to disable the hardware page aggregation at
EL3 by setting CPUECTLR_EL1[46] = 1'b1.

Public Documentation:
https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-5660

Change-Id: Ia59452ea38c66b291790956d7f2880bfcd56d45f
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(cpus): workaround for CVE-2024-5660 for Cortex-A78_AE

Implements mitigation for CVE-2024-5660 that affects Cortex-A78_AE
revisions r0p0, r0p1, r0p2, r0p3.
The workaround is to disable the hardwa

fix(cpus): workaround for CVE-2024-5660 for Cortex-A78_AE

Implements mitigation for CVE-2024-5660 that affects Cortex-A78_AE
revisions r0p0, r0p1, r0p2, r0p3.
The workaround is to disable the hardware page aggregation at
EL3 by setting CPUECTLR_EL1[46] = 1'b1.

Public Documentation:
https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-5660

Change-Id: I33ac653fcb45f687fe9ace1c76a3eb2000459751
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(cpus): workaround for CVE-2024-5660 for Cortex-A78C

Implements mitigation for CVE-2024-5660 that affects Cortex-A78C
revisions r0p0, r0p1, r0p2.
The workaround is to disable the hardware page ag

fix(cpus): workaround for CVE-2024-5660 for Cortex-A78C

Implements mitigation for CVE-2024-5660 that affects Cortex-A78C
revisions r0p0, r0p1, r0p2.
The workaround is to disable the hardware page aggregation at
EL3 by setting CPUECTLR_EL1[46] = 1'b1.

Public Documentation:
https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-5660

Change-Id: Ieb8d7b122320d16bf8987a43dc683ca41227beb5
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(cpus): workaround for CVE-2024-5660 for Cortex-A78

Implements mitigation for CVE-2024-5660 that affects Cortex-A78
revisions r0p0, r1p0, r1p1, r1p2.
The workaround is to disable the hardware pag

fix(cpus): workaround for CVE-2024-5660 for Cortex-A78

Implements mitigation for CVE-2024-5660 that affects Cortex-A78
revisions r0p0, r1p0, r1p1, r1p2.
The workaround is to disable the hardware page aggregation at
EL3 by setting CPUECTLR_EL1[46] = 1'b1.

Public Documentation:
https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-5660

Change-Id: I4e40388bef814481943b2459fe35dd7267c625a2
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(cpus): workaround for CVE-2024-5660 for Cortex-X1

Implements mitigation for CVE-2024-5660 that affects Cortex-X1
revisions r0p0, r1p0, r1p1, r1p2.
The workaround is to disable the hardware page

fix(cpus): workaround for CVE-2024-5660 for Cortex-X1

Implements mitigation for CVE-2024-5660 that affects Cortex-X1
revisions r0p0, r1p0, r1p1, r1p2.
The workaround is to disable the hardware page aggregation at
EL3 by setting CPUECTLR_EL1[46] = 1'b1.

Public Documentation:
https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-5660

Change-Id: I3124db3980f2786412369a010ca6abbbbaa3b601
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(cpus): workaround for CVE-2024-5660 for Neoverse-N2

Implements mitigation for CVE-2024-5660 that affects Neoverse-N2
revisions r0p0, r0p1, r0p2, r0p3.
The workaround is to disable the hardware p

fix(cpus): workaround for CVE-2024-5660 for Neoverse-N2

Implements mitigation for CVE-2024-5660 that affects Neoverse-N2
revisions r0p0, r0p1, r0p2, r0p3.
The workaround is to disable the hardware page aggregation at
EL3 by setting CPUECTLR_EL1[46] = 1'b1.
This patch implements the erratum mitigation for Neoverse-N2.

Public Documentation:
https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-5660

Change-Id: I2b9dea78771cc159586a03ff563c0ec79591ea64
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(cpus): workaround for CVE-2024-5660 for Cortex-A710

Implements mitigation for CVE-2024-5660 that affects Cortex-A710
revisions r0p0, r1p0, r2p0, r2p1.
The workaround is to disable the hardware p

fix(cpus): workaround for CVE-2024-5660 for Cortex-A710

Implements mitigation for CVE-2024-5660 that affects Cortex-A710
revisions r0p0, r1p0, r2p0, r2p1.
The workaround is to disable the hardware page aggregation at
EL3 by setting CPUECTLR_EL1[46] = 1'b1.

Public Documentation:
https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-5660

Change-Id: I10feea238600dcceaac7bb75a59db7913ca65cf1
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(cpus): workaround for CVE-2024-5660 for Neoverse-V2

Implements mitigation for CVE-2024-5660 that affects Neoverse-V2
revisions r0p0, r0p1, r0p2.
The workaround is to disable the hardware page ag

fix(cpus): workaround for CVE-2024-5660 for Neoverse-V2

Implements mitigation for CVE-2024-5660 that affects Neoverse-V2
revisions r0p0, r0p1, r0p2.
The workaround is to disable the hardware page aggregation at
EL3 by setting CPUECTLR_EL1[46] = 1'b1.

Public Documentation:
https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-5660

Change-Id: If66687add52d16f68ce54fe5433dd3b3f067ee04
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(cpus): workaround for CVE-2024-5660 for Cortex-X3

Implements mitigation for CVE-2024-5660 that affects Cortex-X3
revisions r0p0, r1p0, r1p1, r1p2.
The workaround is to disable the hardware page

fix(cpus): workaround for CVE-2024-5660 for Cortex-X3

Implements mitigation for CVE-2024-5660 that affects Cortex-X3
revisions r0p0, r1p0, r1p1, r1p2.
The workaround is to disable the hardware page aggregation at
EL3 by setting CPUECTLR_EL1[46] = 1'b1.

Public Documentation:
https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-5660

Change-Id: Ibe90313948102ece3469f2cfe3faccc7f4beeabe
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(cpus): workaround for CVE-2024-5660 for Neoverse-V3

Implements mitigation for CVE-2024-5660 that affects Neoverse-V3
revisions r0p0, r0p1.
The workaround is to disable the hardware page aggregat

fix(cpus): workaround for CVE-2024-5660 for Neoverse-V3

Implements mitigation for CVE-2024-5660 that affects Neoverse-V3
revisions r0p0, r0p1.
The workaround is to disable the hardware page aggregation at
EL3 by setting CPUECTLR_EL1[46] = 1'b1.

Public Documentation:
https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-5660

Change-Id: I9ed2590bf1215bf6a692f01dfd351e469ff072f8
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(cpus): workaround for CVE-2024-5660 for Cortex-X4

Implements mitigation for CVE-2024-5660 that affects Cortex-X4
revisions r0p0, r0p1, r0p2.
The workaround is to disable the hardware page aggreg

fix(cpus): workaround for CVE-2024-5660 for Cortex-X4

Implements mitigation for CVE-2024-5660 that affects Cortex-X4
revisions r0p0, r0p1, r0p2.
The workaround is to disable the hardware page aggregation at
EL3 by setting CPUECTLR_EL1[46] = 1'b1.

Public Documentation:
https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-5660

Change-Id: I378cb4978919cced03e7febc2ad431c572eac72d
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(pubsub): make sure LTO doesn't garbage collect the handlers

We never directly reference the event handlers so they look like fair
game to be garbage collected when building with LTO.

Tell the c

fix(pubsub): make sure LTO doesn't garbage collect the handlers

We never directly reference the event handlers so they look like fair
game to be garbage collected when building with LTO.

Tell the compiler that we definitely need them and to leave them alone.

Change-Id: Iac672ce85e20328d25acbc3f5e544ad157eebf48
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(css): turn the redistributor off on PSCI CPU_OFF

When GICR_WAKER.ProcessorSleep == 1 (i.e. after gicv3_cpuif_disable())
the GIC will assert the WakeRequest signal to try and wake the core up
ins

fix(css): turn the redistributor off on PSCI CPU_OFF

When GICR_WAKER.ProcessorSleep == 1 (i.e. after gicv3_cpuif_disable())
the GIC will assert the WakeRequest signal to try and wake the core up
instead of delivering an interrupt. This is useful when a core is in
some kind of suspend state.

However, when the core is properly off (CPU_OFF), it shouldn't get woken
up in any way other than a CPU_ON call. In the general case interrupts
would be routed away so this doesn't matter. But in case they aren't, we
want the core to stay off.

So turn the redistributor off on CPU_OFF calls. This will prevent the
WakeRequest from being sent.

Change-Id: I7f20591d1c83a4a9639281ef86caa79d6669b536
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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chore: drop -fno-builtin

It is implied by -ffreestanding

Change-Id: Ia7b0f78fd4020aceea246d10ac3d869e743e7a9f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

Merge "fix(psa): increase psa-mbedtls heap size for rsa" into integration

Merge "fix(cm): fix context management SYSREG128 write macros" into integration

Merge changes from topic "gerrit-master-v3" into integration

* changes:
feat(qemu-sbsa): add support for RME on SBSA machine
feat(qemu-sbsa): configure RMM manifest based on system RAM
feat(qe

Merge changes from topic "gerrit-master-v3" into integration

* changes:
feat(qemu-sbsa): add support for RME on SBSA machine
feat(qemu-sbsa): configure RMM manifest based on system RAM
feat(qemu-sbsa): configure GPT based on system RAM
feat(qemu-sbsa): adjust DT memory start address when supporting RME
feat(qemu-sbsa): relocate DT after the RMM when RME is enabled
feat(qemu-sbsa): dissociate QEMU NS start address and NS_DRAM0_BASE
feat(qemu-sbsa): increase maximum FIP size
refactor(qemu-sbsa): move all DT related functions to sbsa_platform.c
refactor(qemu-sbsa): create accessor functions for platform info
refactor(qemu-sbsa): rename function sip_svc_init() to something more meaningful
refactor(qemu-sbsa): move DT related structures to their own header
refactor(qemu-sbsa): rename struct dynamic_platform_info
refactor(qemu): make L0GPT size configurable
refactor(qemu): move GPT setup to BL31
fix(qemu-sbsa): fix compilation error when accessing DT functions

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Merge "feat(mt8196): enable DP and eDP for mt8196" into integration

Merge "fix(encrypt-fw): put build_msg under LOG_LEVEL flag" into integration

fix(cm): fix context management SYSREG128 write macros

This patch fixes a bug which was introduced in commit
3065513 related to improper saving of EL1 context in the
context management library code

fix(cm): fix context management SYSREG128 write macros

This patch fixes a bug which was introduced in commit
3065513 related to improper saving of EL1 context in the
context management library code when using 128-bit
system registers.

Bug explanation:
The function el1_sysregs_context_save still used the normal
macros that read all the system registers related to the EL1
context, which then involved casting them to uint64_t and
eventually writing them to a memory structure. This means that
the context management library was saving EL1-related SYSREG128
registers with the upper 64 bits zeroed out.

Alternative macros had previously been introduced for the EL2
context in the aforementioned commit, but not for EL1.

Some refactoring has also been done as part of this patch:
- Re-added "common" back to write_el2_ctx_common_sysreg128
- Added dummy SYSREG128 macros for cases when some features
are disabled
- Removed some newlines

Change-Id: I15aa2190794ac099a493e5f430220b1c81e1b558
Signed-off-by: Igor Podgainõi <igor.podgainoi@arm.com>

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