feat(tc): print ni-tower discovery tree

print ni-tower discovery tree to understand ni-tower hierarchy which
might be useful during debugging.

Change-Id: Ib49fef9c63f7740e04b4d8371c1083bd040f6e09
S

feat(tc): print ni-tower discovery tree

print ni-tower discovery tree to understand ni-tower hierarchy which
might be useful during debugging.

Change-Id: Ib49fef9c63f7740e04b4d8371c1083bd040f6e09
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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fix(tc): set console baurate to 38400 for fvp as well

Set console baurate to 38400 for fvp as well for code
simplicity.

Change-Id: I58ba6b7043541f6eb67e32257307da4eba0bb28a
Signed-off-by: Jagdish G

fix(tc): set console baurate to 38400 for fvp as well

Set console baurate to 38400 for fvp as well for code
simplicity.

Change-Id: I58ba6b7043541f6eb67e32257307da4eba0bb28a
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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refactor(tc): remove redundant macro UARTCLK_FREQ

remove redundant macro UARTCLK_FREQ and replace it with TC_UARTCLK
in dts.

Change-Id: Id463a9ddc1588278e552ffca3dfb738676229ce7
Signed-off-by: Jagd

refactor(tc): remove redundant macro UARTCLK_FREQ

remove redundant macro UARTCLK_FREQ and replace it with TC_UARTCLK
in dts.

Change-Id: Id463a9ddc1588278e552ffca3dfb738676229ce7
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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Merge "chore(deps): update pytest for cot-dt2c" into integration

feat(smccc): implement SMCCC_ARCH_FEATURE_AVAILABILITY

SMCCC_ARCH_FEATURE_AVAILABILITY [1] is a call to query firmware about
the features it is aware of and enables. This is useful when a feature
is

feat(smccc): implement SMCCC_ARCH_FEATURE_AVAILABILITY

SMCCC_ARCH_FEATURE_AVAILABILITY [1] is a call to query firmware about
the features it is aware of and enables. This is useful when a feature
is not enabled at EL3, eg due to an older FW image, but it is present in
hardware. In those cases, the EL1 ID registers do not reflect the usable
feature set and this call should provide the necessary information to
remedy that.

The call itself is very lightweight - effectively a sanitised read of
the relevant system register. Bits that are not relevant to feature
enablement are masked out and active low bits are converted to active
high.

The implementation is also very simple. All relevant, irrelevant, and
inverted bits combined into bitmasks at build time. Then at runtime the
masks are unconditionally applied to produce the right result. This
assumes that context managers will make sure that disabled features
do not have their bits set and the registers are context switched if
any fields in them make enablement ambiguous.

Features that are not yet supported in TF-A have not been added. On
debug builds, calling this function will fail an assert if any bits that
are not expected are set. In combination with CI this should allow for
this feature to to stay up to date as new architectural features are
added.

If a call for MPAM3_EL3 is made when MPAM is not enabled, the call
will return INVALID_PARAM, while if it is FEAT_STATE_CHECK, it will
return zero. This should be fairly consistent with feature detection.

The bitmask is meant to be interpreted as the logical AND of the
relevant ID registers. It would be permissible for this to return 1
while the ID returns 0. Despite this, this implementation takes steps
not to. In the general case, the two should match exactly.

Finally, it is not entirely clear whether this call replies to SMC32
requests. However, it will not, as the return values are all 64 bits.

[1]: https://developer.arm.com/documentation/den0028/galp1/?lang=en

Co-developed-by: Charlie Bareham <charlie.bareham@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I1a74e7d0b3459b1396961b8fa27f84e3f0ad6a6f

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refactor(cm): clean up per-world context

In preparation for SMCCC_ARCH_FEATURE_AVAILABILITY, it is useful for
context to be directly related to the underlying system. Currently,
certain bits like SC

refactor(cm): clean up per-world context

In preparation for SMCCC_ARCH_FEATURE_AVAILABILITY, it is useful for
context to be directly related to the underlying system. Currently,
certain bits like SCR_EL3.APK are always set with the understanding that
they will only take effect if the feature is present.

However, that is problematic for SMCCC_ARCH_FEATURE_AVAILABILITY (an
SMCCC call to report which features firmware enables), as simply reading
the enable bit may contradict the ID register, like the APK bit above
for a system with no Pauth present.

This patch is to clean up these cases. Add a check for PAuth's presence
so that the APK bit remains unset if not present. Also move SPE and TRBE
enablement to only the NS context. They already only enable the features
for NS only and disable them for Secure and Realm worlds. This change
only makes these worlds' context read 0 for easy bitmasking.

There's only a single snag on SPE and TRBE. Currently, their fields have
the same values and any world asymmetry is handled by hardware. Since we
don't want to do that, the buffers' ownership will change if we just set
the fields to 0 for non-NS worlds. Doing that, however, exposes Secure
state to a potential denial of service attack - a malicious NS can
enable profiling and call an SMC. Then, the owning security state will
change and since no SPE/TRBE registers are contexted, Secure state will
start generating records. Always have NS world own the buffers to
prevent this.

Finally, get rid of manage_extensions_common() as it's just a level of
indirection to enable a single feature.

Change-Id: I487bd4c70ac3e2105583917a0e5499e0ee248ed9
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(stm32mp2-fdts): add STM32MP257F-DK board support

Add STM32MP257F Discovery board support. It embeds a STM32MP257FAL SoC,
with 2GB of LPDDR4, 2*USB typeA, 1*USB3 typeC, 1*ETH, wifi/BT combo,
DSI

feat(stm32mp2-fdts): add STM32MP257F-DK board support

Add STM32MP257F Discovery board support. It embeds a STM32MP257FAL SoC,
with 2GB of LPDDR4, 2*USB typeA, 1*USB3 typeC, 1*ETH, wifi/BT combo,
DSI HDMI, LVDS connector ...

Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Olivier BIDEAU <olivier.bideau@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I95bb84b00eafce8031f26f7243ecc0fce843d170

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fix(stm32mp2-fdts): fix SDMMC slew rate

New slew rate applied.

SDMMC:
- for SD card and eMMC:
- clk at 2.
- cmd and data at 1.
- for Wifi
- clk at 1.
- cmd and data at 0.

SDMMC

fix(stm32mp2-fdts): fix SDMMC slew rate

New slew rate applied.

SDMMC:
- for SD card and eMMC:
- clk at 2.
- cmd and data at 1.
- for Wifi
- clk at 1.
- cmd and data at 0.

SDMMC1:
- for dk board:
- clk at 2.
- cmd and data at 1.
- for eval board:
- clk at 3.
- cmd and data at 2.

Change-Id: I2dfa62aca08a613e0532746050246fc8dc476ff8
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>

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feat(stm32mp2-fdts): add LPDDR4 files

These DT files will be used by STM32MP2 boards. They embed DDR
parameters for LPDDR4 1x16Gb 1*32bits, at 800MHz or 1200MHz.

Signed-off-by: Yann Gautier <yann.g

feat(stm32mp2-fdts): add LPDDR4 files

These DT files will be used by STM32MP2 boards. They embed DDR
parameters for LPDDR4 1x16Gb 1*32bits, at 800MHz or 1200MHz.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I4017e44b3e9d01735d76518666d05405c2bd976b

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chore(deps): update pytest for cot-dt2c

This resolves Dependabot vulnerability alert #19, resolving a DoS issue
in a dependency of pytest.

Change-Id: I2959da88d3d0422e15d25df5820dfd91f474d6ca
Signe

chore(deps): update pytest for cot-dt2c

This resolves Dependabot vulnerability alert #19, resolving a DoS issue
in a dependency of pytest.

Change-Id: I2959da88d3d0422e15d25df5820dfd91f474d6ca
Signed-off-by: Chris Kay <chris.kay@arm.com>

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feat(handoff): common API for TPM event log handoff

Create a common BL2 API to add a TE for TPM event log.

Change-Id: I459e70f40069aa9ea0625977e0bad8ec316439e6
Signed-off-by: Raymond Mao <raymond.m

feat(handoff): common API for TPM event log handoff

Create a common BL2 API to add a TE for TPM event log.

Change-Id: I459e70f40069aa9ea0625977e0bad8ec316439e6
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>

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feat(handoff): transfer entry ID for TPM event log

Add TE ID for TPM event log handoff.

Change-Id: Idbaaeeee59aaee99d6ec75066562702985ef8204
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>

fix(qemu): fix register convention in BL31 for qemu

The commit with Change-Id:Ie417e054a7a4c192024a2679419e99efeded1705
updated the register convention r1/x1 values but missing necessary
changes in

fix(qemu): fix register convention in BL31 for qemu

The commit with Change-Id:Ie417e054a7a4c192024a2679419e99efeded1705
updated the register convention r1/x1 values but missing necessary
changes in BL31.
As a result, a system panic observed during setup for BL32 when
TRANSFER_LIST is enabled due to unexpected arguments.
This patch is to fix this issue for qemu.

Change-Id: I42e581c5026f0f66d3b114204b4dff167a9bc6ae
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>

show more ...

fix(handoff): fix register convention in opteed

The commit with Change-Id:Ie417e054a7a4c192024a2679419e99efeded1705
updated the register convention r1/x1 values but missing necessary
changes in BL31

fix(handoff): fix register convention in opteed

The commit with Change-Id:Ie417e054a7a4c192024a2679419e99efeded1705
updated the register convention r1/x1 values but missing necessary
changes in BL31.
As a result, a system panic observed during setup for BL32 when
TRANSFER_LIST is enabled due to unexpected arguments.
This patch is to fix this issue for optee.

Change-Id: I13e116e7cb5a7d89fafc11d20295cffbf24793ab
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>

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refactor(cm): change owning security state when a feature is disabled

SPE and TRBE don't have an outright EL3 disable, there are only
constraints on what's allowed. Since we only enable them for NS

refactor(cm): change owning security state when a feature is disabled

SPE and TRBE don't have an outright EL3 disable, there are only
constraints on what's allowed. Since we only enable them for NS at the
moment, we want NS to own the buffers even when the feature should be
"disabled" for a world. This means that when we're running in NS
everything is as normal but when running in S/RL then tracing is
prohibited (since the buffers are owned by NS). This allows us to fiddle
with context a bit more without having to context switch registers.

Change-Id: Ie1dc7c00e4cf9bcc746f02ae43633acca32d3758
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(ff-a): add FFA_MEM_PERM_GET/SET_SMC64

FF-A memory management protocol v1.1 specifies not only
FFA_MEM_PERM_GET_SMC32/FFA_MEM_PERM_SET_SMC32 but also
FFA_MEM_PERM_GET_SMC64/FFA_MEM_PERM_SET_SMC6

feat(ff-a): add FFA_MEM_PERM_GET/SET_SMC64

FF-A memory management protocol v1.1 specifies not only
FFA_MEM_PERM_GET_SMC32/FFA_MEM_PERM_SET_SMC32 but also
FFA_MEM_PERM_GET_SMC64/FFA_MEM_PERM_SET_SMC64.

Change former FFA_MEM_PERM_GET/SET definitions to separate operations
and add handler for FFA_MEM_PERM_GET/SET_SMC64 in spmc_smc_handler().

Signed-off-by: Levi Yun <yeoreum.yun@arm.com>
Change-Id: I175063654703db26c1ffc3cfd7fa428b94d2bfc9

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feat(el3-spmc): support Hob list to boot S-EL0 SP

The EDKII/StandaloneMm module runs as a S-EL0 partition
on top of the EL3 FF-A SPMC.

In the past the StandaloneMm partition received its boot infor

feat(el3-spmc): support Hob list to boot S-EL0 SP

The EDKII/StandaloneMm module runs as a S-EL0 partition
on top of the EL3 FF-A SPMC.

In the past the StandaloneMm partition received its boot information through
the use of a device tree (DT) passed through the FF-A boot protocol.
The StandaloneMm itself converted the DT into a HOB.

To better match the UEFI PI spec,
the EL3 SPMC must now produce the HOB including the PHIT
(Phase Handoff Information Table) as first item in the HOB list.
The SPMC then passes the HOB through the FF-A boot protocol for
the StandaloneMm consumption.

This discards the use of a DT between the SPMC and
the StandaloneMm partition.

Signed-off-by: Levi Yun <yeoreum.yun@arm.com>
Change-Id: I22fb02c710169bd5a5ba1d1f60dce977a5a59ab6

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feat(synquacer): add support Hob creation

When StandaloneMm used with SPM_MM, TF-A should create
PHIT Hob to boot it.
This patch supports Hob creation for StandaloneMm in synquacer platform.

Signed

feat(synquacer): add support Hob creation

When StandaloneMm used with SPM_MM, TF-A should create
PHIT Hob to boot it.
This patch supports Hob creation for StandaloneMm in synquacer platform.

Signed-off-by: Levi Yun <yeoreum.yun@arm.com>
Change-Id: Ifa3ae1f0aa37f389aabb14f48be307502ae6fc2c

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fix(fvp): exclude extend memory map TZC regions

The commit
192287523350 ("fix(spm-mm): carve out NS buffer TZC400 region")
removes overlaps of ns shared buffer in secure memory region.
Unfortunate

fix(fvp): exclude extend memory map TZC regions

The commit
192287523350 ("fix(spm-mm): carve out NS buffer TZC400 region")
removes overlaps of ns shared buffer in secure memory region.
Unfortunately, this separation increases 1 region and over maximum
number of TZC programmable regions when they include
extended memory map regions (DRAM3 to DRAM6).

This causes boot failure of StandaloneMm with spmc_el3 && sp_el0 with

ASSERT: drivers/arm/tzc/tzc400.c:256.

To fix this, like SPM_MM, exclude setting extended memory map regions when
it uses SPMC_AT_EL3 && SPC_AT_EL3_SEL0_SP.

Signed-off-by: Levi Yun <yeoreum.yun@arm.com>
Change-Id: I2d40bea066ca030050dfe951218cd17171010676

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feat(fvp): add StandaloneMm manifest in fvp

Support StandaloneMm running with FF-A as S-EL0 SP
when TF-A is built with EL3 SPMC partition manager.

For this
1. add manifest file describing Stand

feat(fvp): add StandaloneMm manifest in fvp

Support StandaloneMm running with FF-A as S-EL0 SP
when TF-A is built with EL3 SPMC partition manager.

For this
1. add manifest file describing StandaloneMm partition.
2. add number of page mapping area.
3. StandaloneMm should use SRAM with 512K.

while enabling, StandaloneMm, BL1 image requires more size:
aarch64-none-elf/bin/ld: BL31 image has exceeded its limit.
aarch64-none-elf/bin/ld: region `RAM' overflowed by 16384 bytes

So, when using SRAM size with 512K configuration,
increase size limit of BL1 binary.

Signed-off-by: Levi Yun <yeoreum.yun@arm.com>
Change-Id: Idaa1db510340ebb812cfd13588610b2eea941918

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feat(spm): use xfer list with Hob list in SPM_MM

According to Platform Initialization (PI) Specification [1] and
Discussion on edk2 mailing list [2],
StandaloneMm shouldn't create Hob but it should

feat(spm): use xfer list with Hob list in SPM_MM

According to Platform Initialization (PI) Specification [1] and
Discussion on edk2 mailing list [2],
StandaloneMm shouldn't create Hob but it should be passed from TF-A.
IOW, TF-A should pass boot information via PHIT Hob to initialise
StandaloneMm properly.

This patch applies using transfer list with PHIT Hob list [3] for
delivering boot information to StandaloneMm.

Link: https://uefi.org/sites/default/files/resources/PI_Spec_1_6.pdf [1]
Link: https://edk2.groups.io/g/devel/topic/103675962#114283 [2]
Link: https://github.com/FirmwareHandoff/firmware_handoff [3]
Signed-off-by: Levi Yun <yeoreum.yun@arm.com>
Change-Id: I3df71a7679abf9859612afc8a5be7b2381007311

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fix(rme): remove ENABLE_PIE restriction

The combination of ENABLE_RME=1 + ENABLE_PIE=1 build options is
prevented currently for no good reason. ENABLE_PIE in a 4 worlds
configuration is mostly for b

fix(rme): remove ENABLE_PIE restriction

The combination of ENABLE_RME=1 + ENABLE_PIE=1 build options is
prevented currently for no good reason. ENABLE_PIE in a 4 worlds
configuration is mostly for building BL31 with PIE support.
BL1 / BL2 (BL2_RUNS_AT_EL3=1) remain non-PIE. BL32 (TSP) is PIE capable
but typically unused in this configuration. TRP doesn't support PIE
but is loaded in place so isn't affected by this option.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ia60e295534a92cb1b4e3eb88b3e240aea4f4fe1d

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Merge "chore(deps): bump jinja2 in the pip group across 1 directory" into integration

fix(morello): remove stray white-space in 'morello/platform.mk'

Stray white-space in 'morello/platform.mk' to fix the
following compilation error:

$ make PLAT=morello TARGET_PLATFORM=2 all
plat/a

fix(morello): remove stray white-space in 'morello/platform.mk'

Stray white-space in 'morello/platform.mk' to fix the
following compilation error:

$ make PLAT=morello TARGET_PLATFORM=2 all
plat/arm/board/morello/platform.mk:9: *** recipe commences
before first target. Stop.

Fix the same.

While at it also update the year range in the
'Copyright' field.

Change-Id: Id05e4968952049df5ffbe0d25dd17f3aa3a035f7
Signed-off-by: Bhupesh Sharma <Bhupesh.Sharma@arm.com>

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chore(deps): bump jinja2 in the pip group across 1 directory

Bumps the pip group with 1 update in the / directory: [jinja2](https://github.com/pallets/jinja).

Updates `jinja2` from 3.1.4 to 3.1.5
-

chore(deps): bump jinja2 in the pip group across 1 directory

Bumps the pip group with 1 update in the / directory: [jinja2](https://github.com/pallets/jinja).

Updates `jinja2` from 3.1.4 to 3.1.5
- [Release notes](https://github.com/pallets/jinja/releases)
- [Changelog](https://github.com/pallets/jinja/blob/main/CHANGES.rst)
- [Commits](https://github.com/pallets/jinja/compare/3.1.4...3.1.5)

---
updated-dependencies:
- dependency-name: jinja2
dependency-type: indirect
dependency-group: pip
...

Change-Id: I4502ed17a6ce37f53ac64370a5d7fe756875fee6
Signed-off-by: dependabot[bot] <support@github.com>
Signed-off-by: Chris Kay <chris.kay@arm.com>

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