Merge changes from topic "handoff_tpm_event_log" into integration

* changes:
feat(qemu): hand off TPM event log via TL
feat(handoff): common API for TPM event log handoff
feat(handoff): transf

Merge changes from topic "handoff_tpm_event_log" into integration

* changes:
feat(qemu): hand off TPM event log via TL
feat(handoff): common API for TPM event log handoff
feat(handoff): transfer entry ID for TPM event log
fix(qemu): fix register convention in BL31 for qemu
fix(handoff): fix register convention in opteed

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Merge "fix(qemu): fix RMM manifest checksum calculation" into integration

fix(qemu): fix RMM manifest checksum calculation

Commit 71c4443886ff ("fix(lib/rmm_el3_ifc): add console name to checksum
calculation") on TF-RMM updated the checksum calcualtion of the RMM
manifest

fix(qemu): fix RMM manifest checksum calculation

Commit 71c4443886ff ("fix(lib/rmm_el3_ifc): add console name to checksum
calculation") on TF-RMM updated the checksum calcualtion of the RMM
manifest to include the console names.

Include console names in the QEMU manifest to remain compatible with
RMM, just like commit aa99881d3011 ("fix(rme): add console name to
checksum calculation") did for FVP.

Checksum calculation is done by adding together 64-bit values. Add a
helper that does this.

Change-Id: Ica6cab628160593830270bef1acdeb475d1c0c36
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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Merge changes from topic "bk/smccc_feature" into integration

* changes:
feat(smccc): implement SMCCC_ARCH_FEATURE_AVAILABILITY
refactor(cm): clean up per-world context
refactor(cm): change own

Merge changes from topic "bk/smccc_feature" into integration

* changes:
feat(smccc): implement SMCCC_ARCH_FEATURE_AVAILABILITY
refactor(cm): clean up per-world context
refactor(cm): change owning security state when a feature is disabled

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fix(tc): modify ethernet configuration for TC4 FPGA

Modify ethernet base addr and irq numbers for TC4 FPGA in dts to match
with its RoS configuration.

Change-Id: I7b180c3eb90d7557d0011a25a742106f70

fix(tc): modify ethernet configuration for TC4 FPGA

Modify ethernet base addr and irq numbers for TC4 FPGA in dts to match
with its RoS configuration.

Change-Id: I7b180c3eb90d7557d0011a25a742106f703cd264
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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fix(tc): modify gpio controller base addr for TC4 FPGA

Modify gpio controller base addr for TC4 FPGA in dts to match
with its RoS configuration.

Change-Id: Id4ad925d23937d302adfb3e0d4b1573e5ec717c1

fix(tc): modify gpio controller base addr for TC4 FPGA

Modify gpio controller base addr for TC4 FPGA in dts to match
with its RoS configuration.

Change-Id: Id4ad925d23937d302adfb3e0d4b1573e5ec717c1
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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fix(tc): modify DPU configuration in dts for TC4 FPGA

TC4 FPGA DPU base addr and irq doesn't match with TC3 FPGA
so refactor the code to manage it accordingly.

Change-Id: Ie31933e0bcbd4899459358299

fix(tc): modify DPU configuration in dts for TC4 FPGA

TC4 FPGA DPU base addr and irq doesn't match with TC3 FPGA
so refactor the code to manage it accordingly.

Change-Id: Ie31933e0bcbd489945935829940a5c5434e6b1d7
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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fix(tc): modify mmc configuration for TC4 FPGA

Modify mmc base addr and irq numbers for TC4 FPGA in dts to match
with its RoS configuration.

Change-Id: Ie8fe1f1d3aef1c020ac85db7c3b81dfad3722e2f
Sig

fix(tc): modify mmc configuration for TC4 FPGA

Modify mmc base addr and irq numbers for TC4 FPGA in dts to match
with its RoS configuration.

Change-Id: Ie8fe1f1d3aef1c020ac85db7c3b81dfad3722e2f
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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feat(tc): configure UART for TC4 FPGA

TC4 FPGA have a UART clock of 4000000 so modify the value
of TC_UARTCLK for TC4.

Change-Id: I8de84d58bce8b7277bf356136a5185c008ab4c28
Signed-off-by: Jagdish Ge

feat(tc): configure UART for TC4 FPGA

TC4 FPGA have a UART clock of 4000000 so modify the value
of TC_UARTCLK for TC4.

Change-Id: I8de84d58bce8b7277bf356136a5185c008ab4c28
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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feat(mt8196): add Mediatek EMI stub implementation for mt8196

Implement stub functions for the EMI driver to ensure that the build
can pass when a prebuilt library is not available.

Change-Id: I296

feat(mt8196): add Mediatek EMI stub implementation for mt8196

Implement stub functions for the EMI driver to ensure that the build
can pass when a prebuilt library is not available.

Change-Id: I296945a3df6766a3a133cd385a1e5038ca979403
Signed-off-by: Gavin Liu <gavin.liu@mediatek.corp-partner.google.com>

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Merge changes I1f662f82,I59a3b297 into integration

* changes:
fix(build): include platform mk earlier
fix(arm): use EL3_PAS in MAP_BL2_TOTAL definition

feat(gxl): add support for booting from U-Boot SPL/with standard params

The arguments struct needs to be changed to remove a non-standard entry
(`scp_image_info[]`) and also makes use of a built-in

feat(gxl): add support for booting from U-Boot SPL/with standard params

The arguments struct needs to be changed to remove a non-standard entry
(`scp_image_info[]`) and also makes use of a built-in arguments parser.
Since the `scp_image_info[]` entry is removed in U-Boot SPL-compatible builds,
SCP_BL2 image info is hardcoded.

Change-Id: Id3cc887c61c3b940c8a21d9da7f2b6845da51af8
Signed-off-by: Ferass El Hafidi <funderscore@postmarketos.org>

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fix(tc): set system-coherency to 0(ACE-LITE) for tc4-gpu

As per GPU team, this change should be helpful to improve
the performance.

Change-Id: I10a3fc1d0ddf1ba0a17da6dc4f2a80f5fe567db6
Signed-off-b

fix(tc): set system-coherency to 0(ACE-LITE) for tc4-gpu

As per GPU team, this change should be helpful to improve
the performance.

Change-Id: I10a3fc1d0ddf1ba0a17da6dc4f2a80f5fe567db6
Signed-off-by: Vishnu Satheesh <vishnu.satheesh@arm.com>
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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fix(tc): fix SMMU streamId for tc4 gpu

Currently used stream id 0x200 gives below fault,

[ 9.547393][ C0] mali 2d000000.gpu: Unexpected Page fault in firmware address space at VA 0x0000000000

fix(tc): fix SMMU streamId for tc4 gpu

Currently used stream id 0x200 gives below fault,

[ 9.547393][ C0] mali 2d000000.gpu: Unexpected Page fault in firmware address space at VA 0x0000000000000000
[ 9.547393][ C0] raw fault status: 0x400D02C0
[ 9.547393][ C0] exception type 0xC0: TRANSLATION_FAULT at level 0
[ 9.547393][ C0] access type 0x2: READ

As per the GPU team, GPU stream id is 0 on TC4-FPGA so change it.

Change-Id: I3aed62289c5b96fb850f0022ea7f5172c606eb95
Signed-off-by: Vishnu Satheesh <vishnu.satheesh@arm.com>
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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Merge "feat(tc): print ni-tower discovery tree" into integration

Merge changes I58ba6b70,Id463a9dd into integration

* changes:
fix(tc): set console baurate to 38400 for fvp as well
refactor(tc): remove redundant macro UARTCLK_FREQ

Merge "chore(deps): bump jinja2" into integration

fix(smmu): set root port CR0 GPCEN before ACCESSEN

In the SMMU root port programming model, changing both
SMMU_ROOT_CR0.GPCEN and ACCESSEN bits in the same MMIO write operation
is permitted by the a

fix(smmu): set root port CR0 GPCEN before ACCESSEN

In the SMMU root port programming model, changing both
SMMU_ROOT_CR0.GPCEN and ACCESSEN bits in the same MMIO write operation
is permitted by the architecture but left to the SMMU IP implementation
to determine the order of completing one or the other operation.

Enforce more determinism by setting CR0.GPCEN, wait for CR0ACK.GPCEN
completion, then setting CR0.ACCESSEN and wait for CR0ACK.ACCESSEN
completion.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I36ba5fbc13d06c6243226008d18a2d57477b0d28

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chore(deps): bump jinja2

Bumps the pip group with 1 update in the /tools/tlc directory: [jinja2](https://github.com/pallets/jinja).

Updates `jinja2` from 3.1.4 to 3.1.5
- [Release notes](https://gi

chore(deps): bump jinja2

Bumps the pip group with 1 update in the /tools/tlc directory: [jinja2](https://github.com/pallets/jinja).

Updates `jinja2` from 3.1.4 to 3.1.5
- [Release notes](https://github.com/pallets/jinja/releases)
- [Changelog](https://github.com/pallets/jinja/blob/main/CHANGES.rst)
- [Commits](https://github.com/pallets/jinja/compare/3.1.4...3.1.5)

---
updated-dependencies:
- dependency-name: jinja2
dependency-type: direct:production
dependency-group: pip
...

Change-Id: Ib7988c4ee21d6125c073d5b27241921b53a6cac4
Signed-off-by: dependabot[bot] <support@github.com>
Signed-off-by: Chris Kay <chris.kay@arm.com>

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fix(build): include platform mk earlier

Move platform.mk inclusion in top level Makefile to permit a platform
specifying BRANCH_PROTECTION option.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.

fix(build): include platform mk earlier

Move platform.mk inclusion in top level Makefile to permit a platform
specifying BRANCH_PROTECTION option.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I1f662f82cd949eedfdbb61b9f66de15c46fb3106

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fix(arm): use EL3_PAS in MAP_BL2_TOTAL definition

Similarly to BL1 and BL31, use EL3_PAS macro from xlat_tables header
(depends on ENABLE_RME) in BL2 to define MAP_BL2_TOTAL.

Signed-off-by: Olivier

fix(arm): use EL3_PAS in MAP_BL2_TOTAL definition

Similarly to BL1 and BL31, use EL3_PAS macro from xlat_tables header
(depends on ENABLE_RME) in BL2 to define MAP_BL2_TOTAL.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I59a3b297efd2eacd082a297de6b579b7c9052883

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Merge "chore(deps): bump cross-spawn" into integration

Merge "fix(rme): remove ENABLE_PIE restriction" into integration

chore(deps): bump cross-spawn

Bumps the npm_and_yarn group with 1 update in the / directory: [cross-spawn](https://github.com/moxystudio/node-cross-spawn).

Updates `cross-spawn` from 7.0.3 to 7.0.6

chore(deps): bump cross-spawn

Bumps the npm_and_yarn group with 1 update in the / directory: [cross-spawn](https://github.com/moxystudio/node-cross-spawn).

Updates `cross-spawn` from 7.0.3 to 7.0.6
- [Changelog](https://github.com/moxystudio/node-cross-spawn/blob/master/CHANGELOG.md)
- [Commits](https://github.com/moxystudio/node-cross-spawn/compare/v7.0.3...v7.0.6)

---
updated-dependencies:
- dependency-name: cross-spawn
dependency-type: indirect
dependency-group: npm_and_yarn
...

Change-Id: I78624d7ef8c3842a2271d091bf2d3213d9455d87
Signed-off-by: dependabot[bot] <support@github.com>
Signed-off-by: Chris Kay <chris.kay@arm.com>

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feat(qemu): hand off TPM event log via TL

If TRANSFER_LIST is enabled, hand off TPM event log via TL instead
of DT; otherwise fallback to legacy way if TRANSFER_LIST is off or
errors observed.

More

feat(qemu): hand off TPM event log via TL

If TRANSFER_LIST is enabled, hand off TPM event log via TL instead
of DT; otherwise fallback to legacy way if TRANSFER_LIST is off or
errors observed.

Moreover, for updating the TL from secure to non-secure
memory before existing EL3, replace memcpy with function
transfer_list_relocate() for more accuracy.

Change-Id: I1d6bcf573f91efe99380bc89195198a8583b1def
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>

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