fix(arm): don't race on the build directory

Wait for it to have been created. This is the same issue as
commit db69d118294f08aae86378c98aa082ac73e15b73.

Change-Id: I32bd0c713e2837563d32131fb0beddb5

fix(arm): don't race on the build directory

Wait for it to have been created. This is the same issue as
commit db69d118294f08aae86378c98aa082ac73e15b73.

Change-Id: I32bd0c713e2837563d32131fb0beddb5533c0792
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(armada): don't race on the UART_IMAGE

UART_IMAGE is not set when WTP isn't. The error rules will then provide
a recipe for $(BUILD_PLAT). When building with a lot of cores (64) this
rule might b

fix(armada): don't race on the UART_IMAGE

UART_IMAGE is not set when WTP isn't. The error rules will then provide
a recipe for $(BUILD_PLAT). When building with a lot of cores (64) this
rule might be called before the directory is made, causing a build
failure.

Hoist the definition so that the depended path is correct.

Change-Id: I167e7398e576e667d0c5c1fc0f07ab8c8ef939a8
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes I765a7fa0,Ic33f0b6d,I8d1a88c7,I381f96be,I698fa849, ... into integration

* changes:
fix(cpus): clear CPUPWRCTLR_EL1.CORE_PWRDN_EN_BIT on reset
chore(docs): drop the "wfi" from `pwr_

Merge changes I765a7fa0,Ic33f0b6d,I8d1a88c7,I381f96be,I698fa849, ... into integration

* changes:
fix(cpus): clear CPUPWRCTLR_EL1.CORE_PWRDN_EN_BIT on reset
chore(docs): drop the "wfi" from `pwr_domain_pwr_down_wfi`
chore(psci): drop skip_wfi variable
feat(arm): convert arm platforms to expect a wakeup
fix(cpus): avoid SME related loss of context on powerdown
feat(psci): allow cores to wake up from powerdown
refactor: panic after calling psci_power_down_wfi()
refactor(cpus): undo errata mitigations
feat(cpus): add sysreg_bit_toggle

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fix(qemu): statically allocate bitlocks array

gpt_runtime_init() now takes the bitlock array's address and size as
argument. Rather than reserving space at the end of the L0 GPT for
storing bitlocks

fix(qemu): statically allocate bitlocks array

gpt_runtime_init() now takes the bitlock array's address and size as
argument. Rather than reserving space at the end of the L0 GPT for
storing bitlocks, allocate a static array and pass its address to
gpt_runtime_init(). This frees up a little bit of space formerly
reserved for alignment of the GPT.

Change-Id: I48a1a2bc230f64e13e3ed08b18ebdc2d387d77d0
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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feat(qemu): update for renamed struct memory_bank

The struct ns_dram_bank has been renamed to struct memory_bank, so
update plat/qemu accordingly.

Signed-off-by: Jens Wiklander <jens.wiklander@lina

feat(qemu): update for renamed struct memory_bank

The struct ns_dram_bank has been renamed to struct memory_bank, so
update plat/qemu accordingly.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Change-Id: If5ed92edd132c977009a7371ec53eca0ee35ef00

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feat(fvp): increase GPT PPS to 1TB

- Increase PPS for FVP from 64GB to 1TB.
- GPT L0 table for 1TB PPS requires 8KB memory.
- Set FVP_TRUSTED_SRAM_SIZE to 384 with ENABLE_RME=1
option.
- Add 256MB

feat(fvp): increase GPT PPS to 1TB

- Increase PPS for FVP from 64GB to 1TB.
- GPT L0 table for 1TB PPS requires 8KB memory.
- Set FVP_TRUSTED_SRAM_SIZE to 384 with ENABLE_RME=1
option.
- Add 256MB of PCIe memory region 1 and 3GB of
PCIe memory region 2 to FVP PAS regions array.

Change-Id: Icadd528576f53c55b5d461ff4dcd357429ba622a
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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feat(gpt): statically allocate bitlocks array

Statically allocate 'gpt_bitlock' array of fine-grained
'bitlock_t' data structures in arm_bl31_setup.c.
The amount of memory needed for this array is c

feat(gpt): statically allocate bitlocks array

Statically allocate 'gpt_bitlock' array of fine-grained
'bitlock_t' data structures in arm_bl31_setup.c.
The amount of memory needed for this array is controlled
by 'RME_GPT_BITLOCK_BLOCK' build option and 'PLAT_ARM_PPS'
macro defined in platform_def.h which specifies the size
of protected physical address space in bytes.
'PLAT_ARM_PPS' takes values from 4GB to 4PB supported by
Arm architecture.

Change-Id: Icf620b5039e45df6828d58fca089cad83b0bc669
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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chore(gpt): define PPS in platform header files

Define protected physical address size in bytes
PLAT_ARM_PPS macro for FVP and RDV3 in platform_def.h
files.

Change-Id: I7f6529dfbb8df864091fbefc0813

chore(gpt): define PPS in platform header files

Define protected physical address size in bytes
PLAT_ARM_PPS macro for FVP and RDV3 in platform_def.h
files.

Change-Id: I7f6529dfbb8df864091fbefc08131a0e6d689eb6
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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feat(fvp): allocate L0 GPT at the top of SRAM

This patch allocates level 0 GPT at the top of SRAM
for FVP. This helps to meet L0 GPT alignment requirements
and prevent the occurrence of possible unu

feat(fvp): allocate L0 GPT at the top of SRAM

This patch allocates level 0 GPT at the top of SRAM
for FVP. This helps to meet L0 GPT alignment requirements
and prevent the occurrence of possible unused gaps in SRAM.
Load addresses for FVP TB_FW, SOC_FW and TOS_FW DTBs are
defined in fvp_fw_config.dts via ARM_BL_RAM_BASE macro.

Change-Id: Iaa52e302373779d9fdbaf4e1ba40c10aa8d1f8bd
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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feat(fvp): change size of PCIe memory region 2

Change size of PCIe memory region 2 from 256GB
to 3GB to fit in 1TB of GPT PPS.

Change-Id: Ic769bb784dd17d390b54ccef53b7788334373cb4
Signed-off-by: Al

feat(fvp): change size of PCIe memory region 2

Change size of PCIe memory region 2 from 256GB
to 3GB to fit in 1TB of GPT PPS.

Change-Id: Ic769bb784dd17d390b54ccef53b7788334373cb4
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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feat(rmm): add PCIe IO info to Boot manifest

- Add PCIe and SMMUv3 related information to DTS for
configurations with ENABLE_RME=1.
- Add entries for PCIe IO memory regions to Boot manifest
- Upda

feat(rmm): add PCIe IO info to Boot manifest

- Add PCIe and SMMUv3 related information to DTS for
configurations with ENABLE_RME=1.
- Add entries for PCIe IO memory regions to Boot manifest
- Update RMMD_MANIFEST_VERSION_MINOR from 3 to 4.
- Read PCIe related information from DTB and write it to
Boot manifest.
- Rename structures that used to describe DRAM layout
and now describe both DRAM and PCIe IO memory regions:
- ns_dram_bank -> memory_bank
- ns_dram_info -> memory_info.

Change-Id: Ib75d1af86076f724f5c330074e231f1c2ba8e21d
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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feat(fvp): define single Root region

For FVP model define single Root PAS which
includes EL3 DRAM data, L1 GPTs and SCP TZC.
This allows to decrease the number of PAS
regions passed to GPT library a

feat(fvp): define single Root region

For FVP model define single Root PAS which
includes EL3 DRAM data, L1 GPTs and SCP TZC.
This allows to decrease the number of PAS
regions passed to GPT library and use GPT
mapping with Contiguous descriptor of
larger block size.

Change-Id: I70f6babaebc14e5e0bce033783ec423c8a26c542
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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Merge "fix(mt8196): fix wrong register offset of dptx on MT8196" into integration

Merge "feat(mt8196): enable vcore dvfsrc feature" into integration

chore(dependabot): further refine Dependabot configuration

The current Dependabot configuration results in several breaking changes
to `package.json` and `pyproject.toml` files. Until we can get aro

chore(dependabot): further refine Dependabot configuration

The current Dependabot configuration results in several breaking changes
to `package.json` and `pyproject.toml` files. Until we can get around
bringing all of our tooling up to date with their latest dependencies,
just ask Dependabot to limit its changes to minor updates in the
lockfiles.

Change-Id: I8a161c6373a24ae9b754eab47f04c3c3e85c449c
Signed-off-by: Chris Kay <chris.kay@arm.com>

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fix(drtm): fix DLME data size check

dlme_data_min_size is currently defined in pages but is being compared
against byte sizes in the code. This patch corrects this issue.

Change-Id: Ib250ef6efedf32

fix(drtm): fix DLME data size check

dlme_data_min_size is currently defined in pages but is being compared
against byte sizes in the code. This patch corrects this issue.

Change-Id: Ib250ef6efedf321706624dfca263e8042a25f6d1
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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fix(drtm): sort the address-map in ascending order

As per the specification the address map region in the
DLME data must be sorted.

Change-Id: Ibf39dad33ef7ce739d6ec8632198df55a4e8a1c3
Signed-off-b

fix(drtm): sort the address-map in ascending order

As per the specification the address map region in the
DLME data must be sorted.

Change-Id: Ibf39dad33ef7ce739d6ec8632198df55a4e8a1c3
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(libc): import qsort implementation

Import qsort implementation from FreeBSD[1] to libc.

[1]: https://cgit.freebsd.org/src/tree/lib/libc/stdlib/qsort.c

Change-Id: Ia0d8e2d1c40c679844c0746db1b6

feat(libc): import qsort implementation

Import qsort implementation from FreeBSD[1] to libc.

[1]: https://cgit.freebsd.org/src/tree/lib/libc/stdlib/qsort.c

Change-Id: Ia0d8e2d1c40c679844c0746db1b669cda672a482
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "fix: add support for 128-bit sysregs to EL3 crash handler" into integration

fix(altera): add in support for agilex5 b0 jtag id

Support Agilex5 B0 jtag id for fpga reconfig.

Change-Id: I4efb5a046a0f11009a1f08412ff0e48f376c94e1
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel

fix(altera): add in support for agilex5 b0 jtag id

Support Agilex5 B0 jtag id for fpga reconfig.

Change-Id: I4efb5a046a0f11009a1f08412ff0e48f376c94e1
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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feat(mt8196): enable vcore dvfsrc feature

This patch will enable vcore dvfsrc.
- VCORE DVFS is the feature to change VCORE/DDR Freq for power saving
- When there are no requests for using Vcore/DRAM

feat(mt8196): enable vcore dvfsrc feature

This patch will enable vcore dvfsrc.
- VCORE DVFS is the feature to change VCORE/DDR Freq for power saving
- When there are no requests for using Vcore/DRAM, Vcore DVFS will
- lower the voltage and frequency of Vcore/DRAM to achieve power saving.

Signed-off-by: Kunlong Wang <kunlong.wang@mediatek.corp-partner.google.com>
Change-Id: I972eb2da1b8526f4ce2927cd662a6fc3ef2f2401

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Merge "docs: bump the arm compiler version" into integration

docs: bump the arm compiler version

Patch fdae0b95852e087d8a19187f4d40babc67f0e57a in the CI bumped it to
6.23. Reflect this in docs

Change-Id: I39f3cd6fb03f81066fbbae3672c79802c607e3cd
Signed-off-

docs: bump the arm compiler version

Patch fdae0b95852e087d8a19187f4d40babc67f0e57a in the CI bumped it to
6.23. Reflect this in docs

Change-Id: I39f3cd6fb03f81066fbbae3672c79802c607e3cd
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(mt8196): fix wrong register offset of dptx on MT8196

Fix wrong register offset of dptx on MT8196.

Change-Id: I46f7ac7751d14c9093b7b5bd1c741179a7fbbd34
Signed-off-by: Gavin Liu <gavin.liu@mediat

fix(mt8196): fix wrong register offset of dptx on MT8196

Fix wrong register offset of dptx on MT8196.

Change-Id: I46f7ac7751d14c9093b7b5bd1c741179a7fbbd34
Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>

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Merge "feat(cpus): add ENABLE_ERRATA_ALL flag" into integration