chore(cpus): fix cve order in Neoverse-V2

Patch rearranges CVE-2024-5660 in order based on
the year and index for Neoverse-V2.

Change-Id: I092a93ef3299fd733abae9c462c019f94d881413
Signed-off-by: So

chore(cpus): fix cve order in Neoverse-V2

Patch rearranges CVE-2024-5660 in order based on
the year and index for Neoverse-V2.

Change-Id: I092a93ef3299fd733abae9c462c019f94d881413
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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chore(cpus): rearrange the errata and cve order in Neoverse-N2

Patch sorts the errata IDs in ascending order and the
CVE's in ascending order based on the year and index
for CPU Neoverse N2.

Change

chore(cpus): rearrange the errata and cve order in Neoverse-N2

Patch sorts the errata IDs in ascending order and the
CVE's in ascending order based on the year and index
for CPU Neoverse N2.

Change-Id: Ieb4a8ab0030ea4e83efdef86a0ff1e2990b3e0dd
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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chore(cpus): rearrange the errata and cve in order in Neoverse-V3

Patch sorts the errata IDs in ascending order and the CVE's
in ascending order based on the year and index for Neoverse-V3.

Change-

chore(cpus): rearrange the errata and cve in order in Neoverse-V3

Patch sorts the errata IDs in ascending order and the CVE's
in ascending order based on the year and index for Neoverse-V3.

Change-Id: I108eb2896e24c135d56e5096289766d777b48b48
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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chore(cpus): rearrange the errata and cve in order in Cortex-A710

Patch sorts the errata IDs in ascending order and the
CVE's in ascending order based on the year and index
for CPU Cortex-A710.

Cha

chore(cpus): rearrange the errata and cve in order in Cortex-A710

Patch sorts the errata IDs in ascending order and the
CVE's in ascending order based on the year and index
for CPU Cortex-A710.

Change-Id: Ie7c2b77879f8fa5abb77204678e09cc759b10278
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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chore(cpus): rearrange cve in order in Cortex-X1

Patch rearranges CVE-2024-5660 in ascending order based on
the year and index for Cortex X1.

Change-Id: I0c4206e38f09b1f88ee95e8ce69d7e13b8a9bb2d
Si

chore(cpus): rearrange cve in order in Cortex-X1

Patch rearranges CVE-2024-5660 in ascending order based on
the year and index for Cortex X1.

Change-Id: I0c4206e38f09b1f88ee95e8ce69d7e13b8a9bb2d
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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chore(cpus): fix cve order in Neoverse-V1

This patch rearranges CVE-2024-5660 apply order in Neoverse-V1.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ice0b1c6efa913f885

chore(cpus): fix cve order in Neoverse-V1

This patch rearranges CVE-2024-5660 apply order in Neoverse-V1.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ice0b1c6efa913f88522fb33182b9cdc0e7723988

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chore(cpus): fix cve order in Cortex-X2

This patch rearranges CVE-2024-5660, erratum 2313941
and 3701772 apply order in Cortex-X2.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Chan

chore(cpus): fix cve order in Cortex-X2

This patch rearranges CVE-2024-5660, erratum 2313941
and 3701772 apply order in Cortex-X2.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ie74d7232a14f3cdd14c4d0ffb1ee91b537c491ea

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chore(cpus): fix cve order in Cortex-A78C

This patch rearranges CVE-2024-5660 apply order in Cortex-A78C.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I326be1da279bd34df

chore(cpus): fix cve order in Cortex-A78C

This patch rearranges CVE-2024-5660 apply order in Cortex-A78C.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I326be1da279bd34df8667f7e957fb4a2c6913ab9

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chore(cpus): fix cve order in Cortex-A78_AE

This patch rearranges CVE-2024-5660 apply order in Cortex-A78_AE.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Idfb076b798a84

chore(cpus): fix cve order in Cortex-A78_AE

This patch rearranges CVE-2024-5660 apply order in Cortex-A78_AE.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Idfb076b798a840847c00066bd062ee919369272f

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chore(cpus): fix cve order in Cortex-A78

This patch rearranges CVE-2024-5660 apply order in Cortex-A78.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: If80a0f95f82dbf69100

chore(cpus): fix cve order in Cortex-A78

This patch rearranges CVE-2024-5660 apply order in Cortex-A78.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: If80a0f95f82dbf69100a2687b06db2373a9e9832

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chore(cpus): fix cve order in Cortex-A77

This patch rearranges CVE-2024-5660 apply order in Cortex-A77.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I41d76268ce2248bfd36

chore(cpus): fix cve order in Cortex-A77

This patch rearranges CVE-2024-5660 apply order in Cortex-A77.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I41d76268ce2248bfd3600bbf6b89d16b6bdce8f0

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refactor(cpus): don't panic if errata out of order

Previously we have used enclosed the Errata ordering check
within the FEATURE_DETECTION flag as this flag is only
used for development purpose and

refactor(cpus): don't panic if errata out of order

Previously we have used enclosed the Errata ordering check
within the FEATURE_DETECTION flag as this flag is only
used for development purpose and it also enforces
ordering by causing a panic when the assert fails.
A simple warning message would suffice and hence this
patch removes the assert.

The erratum and cve ordering check is planned to be implemented
in static check at which point the warning will be taken out as well.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I0ffc40361985281163970ea5bc81ca0269b16442

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Merge "fix(plat): remove unused vfp code" into integration

Merge "feat(zynqmp): add pin group for lower qspi interface" into integration

Merge "chore(docs): explain what the plat_amu_aux_enables array does" into integration

Merge "chore(cm): add MDCR_EL3.RLTE to context management" into integration

Merge "fix(rdv3): correctly handle FP regs context saving" into integration

refactor(mediatek): fix mcusys off issue for MTK GIC v3 driver

When mcusys is off, rdist_ctx will save the rdist data of the last core.
In the case of the last core plug off, the data of other cores

refactor(mediatek): fix mcusys off issue for MTK GIC v3 driver

When mcusys is off, rdist_ctx will save the rdist data of the last core.
In the case of the last core plug off, the data of other cores will be
inconsistent with the data in rdist_ctx.

Therefore, each core needs to use a dedicated context.

Signed-off-by: Runyang Chen <runyang.chen@mediatek.com>
Change-Id: Ic9501f4da219cf906c0e348982be3f550c3ba30b

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Merge "feat(lib): implement strnlen secure and strcpy secure function" into integration

feat(fvp): give bootargs on all configs

Linux needs bootargs with or without RME. Have them always on.

Change-Id: I4e7f582862ba9a0a96c0d6de10d021eed51740d6
Signed-off-by: Boyan Karatotev <boyan.kar

feat(fvp): give bootargs on all configs

Linux needs bootargs with or without RME. Have them always on.

Change-Id: I4e7f582862ba9a0a96c0d6de10d021eed51740d6
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(arm): simplify early platform setup functions

Refactor `arm_sp_min_early_platform_setup` to accept generic
`u_register_r` values to support receiving firmware handoff boot
arguments in comm

refactor(arm): simplify early platform setup functions

Refactor `arm_sp_min_early_platform_setup` to accept generic
`u_register_r` values to support receiving firmware handoff boot
arguments in common code. This has the added benefit of simplifying the
interface into common early platform setup.

Change-Id: Idfc3d41f94f2bf3a3a0c7ca39f6b9b0013836e3a
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(rdv3): correctly handle FP regs context saving

Commit fe488c3796e01187fb6cffdd27a1bee1a33e0931 added an override to
force `CTX_INCLUDE_SVE_REGS` to 0 when `SPD == spmd` and
`SPMD_SPM_AT_SEL2 ==

fix(rdv3): correctly handle FP regs context saving

Commit fe488c3796e01187fb6cffdd27a1bee1a33e0931 added an override to
force `CTX_INCLUDE_SVE_REGS` to 0 when `SPD == spmd` and
`SPMD_SPM_AT_SEL2 == 1`.
Since there is an architectural dependency between FP and SVE registers,
`CTX_INCLUDE_FPREGS` must also be overridden to 0 when
CTX_INCLUDE_SVE_REGS is 0.

Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I1cd834241a2d5a5368ac532a348d8729a701bbcd

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Merge "build(poetry): install SP dependencies with `--no-root`" into integration

Merge changes from topic "dtpm_poc" into integration

* changes:
feat(docs): update mboot threat model with dTPM
docs(tpm): add design documentation for dTPM
fix(rpi3): expose BL1_RW to BL2 ma

Merge changes from topic "dtpm_poc" into integration

* changes:
feat(docs): update mboot threat model with dTPM
docs(tpm): add design documentation for dTPM
fix(rpi3): expose BL1_RW to BL2 map for mboot
feat(rpi3): add dTPM backed measured boot
feat(tpm): add Infineon SLB9670 GPIO SPI config
feat(tpm): add tpm drivers and framework
feat(io): add generic gpio spi bit-bang driver
feat(rpi3): implement eventlog handoff to BL33
feat(rpi3): implement mboot for rpi3

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Merge changes from topic "mec" into integration

* changes:
feat(qemu): add plat_rmmd_mecid_key_update()
feat(rmmd): add RMM_MECID_KEY_UPDATE call